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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-429059714d5sm135171295e9.13.2024.08.09.09.04.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Aug 2024 09:04:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1723219477; x=1723824277; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ICJBhRzXeSHxiQ/p/CxRsyTFTBxBWWvxj76zvD9iTsA=; b=b5Abe9i1vt616+EgPJfr4bTfwx8KG3TRTHTadQp6ljSdXsis+pPhd1Fe6kJ/sEzQIP QUT0EXsvuh99U7+S/kQT6gBdsXrRIc37jKRMQPlqToBB+hmQLRcvb5eH1RLbkdYqD7TO 0861UWTULG64oy8KBGI1jHByUqmi3J0Ku+iAphQuUrU3ZOctcbWhiATw0jtQqWvc7AXE 5RgYiikbnc+oKG3lMaF8FxvuyMXbhx8iOnWfhloaCxRdq3qcMB+Dht6jS6IVOmwDAE85 lu1if1B8vB6JzKr3uz8Ym45QZGL7p0nVgiWTpT6ZzLtvzYA7G6lwJ0RfN24GYuPrZdgf htwQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1723219477; x=1723824277; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ICJBhRzXeSHxiQ/p/CxRsyTFTBxBWWvxj76zvD9iTsA=; b=L9fjRV+suR/Qab7mWf87Ym+HE1pX+xBxwbI7E3Mym93POo/wdh1WrSJ1+EWkxgHfbp TyFeIkpUX6HwsfxTlfH2jM4A9ejFu2sfYaEcF7gq9AISbmFRanAMxbgfGBdsAgDLpOgM SfBxoT8234VM2pezFyyGKF7jvKF23SLQ816o1pPqyFdHxP7/h0n/gPWpdxrP+wtoFSAy is1xf4SUYipmxhdAYqLNYQFH9zALgr5zwmHbUCbf31Ik8nezY0X5r7j/EB3xH2CGreLo MRvqu2FMRDeNr2za/e0gz++Rn+LEiydw44NCY13z+d9RCOYiWWQWZg9DS7D4b9hILp1+ nZLw== X-Forwarded-Encrypted: i=1; AJvYcCUYVDoRoHfG9qvIGhgQsQfYzKm1Wk/fR1tUL1QZpu3NqBEXzxIp685b00pvrx4Os3WV4IWYdKkkRmRfiTopwwJQvZf8Lrs= X-Gm-Message-State: AOJu0Yy8miNa4pKxzzViGsCU5tY3TFKlQipEeB1MkCZgIZ8p48JLQLat d25AiQ5Wtd5W1w7OkMyvzYepxE8hKc/b7h9tQXhfBiUIl5Agz44MOKYiu63yFGQ= X-Google-Smtp-Source: AGHT+IGH/XkF6c7YliELRAZ3C+w64+vKTfsT7ki7NvPurtzZwDlBBQtzSBblkJnK83C7QQy3uV09AQ== X-Received: by 2002:a05:6000:b89:b0:368:3b5c:7a5d with SMTP id ffacd0b85a97d-36d5e1c7656mr2289108f8f.20.1723219477084; Fri, 09 Aug 2024 09:04:37 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: qemu-stable@nongnu.org, Bernhard Beschow Subject: [PATCH 1/2] target/arm: Update translation regime comment for new features Date: Fri, 9 Aug 2024 17:04:29 +0100 Message-Id: <20240809160430.1144805-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240809160430.1144805-1-peter.maydell@linaro.org> References: <20240809160430.1144805-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1723219595888116600 Content-Type: text/plain; charset="utf-8" We have a long comment describing the Arm architectural translation regimes and how we map them to QEMU MMU indexes. This comment has got a bit out of date: * FEAT_SEL2 allows Secure EL2 and corresponding new regimes * FEAT_RME introduces Realm state and its translation regimes * We now model the Cortex-R52 so that is no longer a hypothetical * We separated Secure Stage 2 and NonSecure Stage 2 MMU indexes * We have an MMU index per physical address spacea Add the missing pieces so that the list of architectural translation regimes matches the Arm ARM, and the list and count of QEMU MMU indexes in the comment matches the enum. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpu.h | 23 ++++++++++++++++------- 1 file changed, 16 insertions(+), 7 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index a12859fc533..216774f5d3a 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2772,8 +2772,14 @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sy= nc); * + NonSecure EL1 & 0 stage 2 * + NonSecure EL2 * + NonSecure EL2 & 0 (ARMv8.1-VHE) - * + Secure EL1 & 0 - * + Secure EL3 + * + Secure EL1 & 0 stage 1 + * + Secure EL1 & 0 stage 2 (FEAT_SEL2) + * + Secure EL2 (FEAT_SEL2) + * + Secure EL2 & 0 (FEAT_SEL2) + * + Realm EL1 & 0 stage 1 (FEAT_RME) + * + Realm EL1 & 0 stage 2 (FEAT_RME) + * + Realm EL2 (FEAT_RME) + * + EL3 * If EL3 is 32-bit: * + NonSecure PL1 & 0 stage 1 * + NonSecure PL1 & 0 stage 2 @@ -2805,10 +2811,12 @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_s= ync); * table over and over. * 6. we need separate EL1/EL2 mmu_idx for handling the Privileged Access * Never (PAN) bit within PSTATE. - * 7. we fold together the secure and non-secure regimes for A-profile, + * 7. we fold together most secure and non-secure regimes for A-profile, * because there are no banked system registers for aarch64, so the * process of switching between secure and non-secure is * already heavyweight. + * 8. we cannot fold together Stage 2 Secure and Stage 2 NonSecure, + * because both are in use simultaneously for Secure EL2. * * This gives us the following list of cases: * @@ -2820,14 +2828,15 @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_s= ync); * EL2 EL2&0 +PAN * EL2 (aka NS PL2) * EL3 (aka S PL1) - * Physical (NS & S) - * Stage2 (NS & S) + * Stage2 Secure + * Stage2 NonSecure + * plus one TLB per Physical address space: S, NS, Realm, Root * - * for a total of 12 different mmu_idx. + * for a total of 14 different mmu_idx. * * R profile CPUs have an MPU, but can use the same set of MMU indexes * as A profile. They only need to distinguish EL0 and EL1 (and - * EL2 if we ever model a Cortex-R52). + * EL2 for cores like the Cortex-R52). * * M profile CPUs are rather different as they do not have a true MMU. * They have the following different MMU indexes: --=20 2.34.1