From nobody Sun Nov 24 12:43:26 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1723085479; cv=none; d=zohomail.com; s=zohoarc; b=lRYtYvJVVsA9Dkdn+pydBQjQDk2kY8D1Qai1hXtzNwdlyQ0NdyORWpu/nVGgpTLntFEuiFr0s8MuwXvhm70NVicpq5ONStlgkXA9x5sT60HP3v2jBSsHVoZHeox4ESWpazYt3pBmH1GlV4ZrAtmESo+pdHmNtzx6FwwmNG2YPqo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1723085479; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=t//rePLA+k52dBm5d1rFJnXgk6N6lTFGW01h4A4lujw=; b=FhaPfOgDFH9rcDv5qyYLTLjLlJjElwCAHQDA0oW0E1nMxmkqVTotPCQd1TOIwNKWe5yH9FEF2O517Xe0MVcGoZXd55mHqKnZvoV+AJisb194EdEZhZS79++1hEjPUgWe4e6P05mrNe4dh3+q317b3swXmr1QrRJlA+u49fMvids= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1723085479604147.48683779478233; Wed, 7 Aug 2024 19:51:19 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sbtDo-0007py-PM; Wed, 07 Aug 2024 22:49:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sbtDn-0007jx-9X; Wed, 07 Aug 2024 22:49:47 -0400 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sbtDl-0008AE-Q2; Wed, 07 Aug 2024 22:49:47 -0400 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Thu, 8 Aug 2024 10:49:18 +0800 Received: from localhost.localdomain (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Thu, 8 Aug 2024 10:49:18 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , Cleber Rosa , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , "Wainer dos Santos Moschetta" , Beraldo Leal , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , , , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PATCH v2 07/11] hw/i2c/aspeed: support high part dram offset for DMA 64 bits Date: Thu, 8 Aug 2024 10:49:12 +0800 Message-ID: <20240808024916.1262715-8-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240808024916.1262715-1-jamin_lin@aspeedtech.com> References: <20240808024916.1262715-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1723085480454116600 ASPEED AST2700 SOC is a 64 bits quad core CPUs (Cortex-a35) And the base address of dram is "0x4 00000000" which is 64bits address. The AST2700 support the maximum DRAM size is 8 GB. The DRAM physical address range is from "0x4_0000_0000" to "0x5_FFFF_FFFF". The DRAM offset range is from "0x0_0000_0000" to "0x1_FFFF_FFFF" and it is enough to use bits [33:0] saving the dram offset. Therefore, save the high part physical address bit[1:0] of Tx/Rx buffer address as dma_dram_offset bit[33:32]. It does not need to decrease the dram physical high part address for DMA operation. (high part physical address bit[7:0] =E2=80=93 4) Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater --- hw/i2c/aspeed_i2c.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/hw/i2c/aspeed_i2c.c b/hw/i2c/aspeed_i2c.c index c1ff80b1cf..44c3c39233 100644 --- a/hw/i2c/aspeed_i2c.c +++ b/hw/i2c/aspeed_i2c.c @@ -743,6 +743,14 @@ static void aspeed_i2c_bus_new_write(AspeedI2CBus *bus= , hwaddr offset, __func__); break; =20 + /* + * The AST2700 support the maximum DRAM size is 8 GB. + * The DRAM offset range is from 0x0_0000_0000 to + * 0x1_FFFF_FFFF and it is enough to use bits [33:0] + * saving the dram offset. + * Therefore, save the high part physical address bit[1:0] + * of Tx/Rx buffer address as dma_dram_offset bit[33:32]. + */ case A_I2CM_DMA_TX_ADDR_HI: if (!aic->has_dma64) { qemu_log_mask(LOG_GUEST_ERROR, "%s: No DMA 64 bits support\n", @@ -752,6 +760,8 @@ static void aspeed_i2c_bus_new_write(AspeedI2CBus *bus,= hwaddr offset, bus->regs[R_I2CM_DMA_TX_ADDR_HI] =3D FIELD_EX32(value, I2CM_DMA_TX_ADDR_HI, ADDR_HI); + bus->dma_dram_offset =3D deposit64(bus->dma_dram_offset, 32, 32, + extract32(value, 0, 2)); break; case A_I2CM_DMA_RX_ADDR_HI: if (!aic->has_dma64) { @@ -762,6 +772,8 @@ static void aspeed_i2c_bus_new_write(AspeedI2CBus *bus,= hwaddr offset, bus->regs[R_I2CM_DMA_RX_ADDR_HI] =3D FIELD_EX32(value, I2CM_DMA_RX_ADDR_HI, ADDR_HI); + bus->dma_dram_offset =3D deposit64(bus->dma_dram_offset, 32, 32, + extract32(value, 0, 2)); break; case A_I2CS_DMA_TX_ADDR_HI: qemu_log_mask(LOG_UNIMP, @@ -777,6 +789,8 @@ static void aspeed_i2c_bus_new_write(AspeedI2CBus *bus,= hwaddr offset, bus->regs[R_I2CS_DMA_RX_ADDR_HI] =3D FIELD_EX32(value, I2CS_DMA_RX_ADDR_HI, ADDR_HI); + bus->dma_dram_offset =3D deposit64(bus->dma_dram_offset, 32, 32, + extract32(value, 0, 2)); break; default: qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\= n", --=20 2.34.1