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Tue, 06 Aug 2024 17:07:18 -0700 (PDT) From: Deepak Gupta To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: richard.henderson@linaro.org, pbonzini@redhat.com, palmer@dabbelt.com, Alistair.Francis@wdc.com, laurent@vivier.eu, bmeng.cn@gmail.com, liwei1518@gmail.com, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, Deepak Gupta , Jim Shu Subject: [PATCH v3 18/20] target/riscv: add trace-hooks for each case of sw-check exception Date: Tue, 6 Aug 2024 17:06:49 -0700 Message-ID: <20240807000652.1417776-19-debug@rivosinc.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: <20240807000652.1417776-1-debug@rivosinc.com> References: <20240807000652.1417776-1-debug@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=debug@rivosinc.com; helo=mail-pl1-x636.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @rivosinc-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1722989335072116600 Content-Type: text/plain; charset="utf-8" Violations to control flow rules setup by zicfilp and zicfiss lead to software check exceptions. To debug and fix such sw check issues in guest , add trace-hooks for each case. Signed-off-by: Jim Shu Signed-off-by: Deepak Gupta --- target/riscv/insn_trans/trans_rvi.c.inc | 6 ++++-- target/riscv/op_helper.c | 24 ++++++++++++++++++++++++ target/riscv/trace-events | 6 ++++++ target/riscv/translate.c | 2 +- 4 files changed, 35 insertions(+), 3 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_tr= ans/trans_rvi.c.inc index cbd7d5c395..0f5d5def60 100644 --- a/target/riscv/insn_trans/trans_rvi.c.inc +++ b/target/riscv/insn_trans/trans_rvi.c.inc @@ -65,7 +65,8 @@ static bool trans_lpad(DisasContext *ctx, arg_lpad *a) */ gen_helper_raise_sw_check_excep(tcg_env, tcg_constant_tl(RISCV_EXCP_SW_CHECK_FCFI_TVAL), - tcg_constant_tl(MISALIGNED_LPAD), tcg_constant_tl(0)); + tcg_constant_tl(MISALIGNED_LPAD), + tcg_constant_tl(ctx->base.pc_next)); return true; } } @@ -81,7 +82,8 @@ static bool trans_lpad(DisasContext *ctx, arg_lpad *a) tcg_gen_brcondi_tl(TCG_COND_EQ, tmp, a->imm_cfi20, skip); gen_helper_raise_sw_check_excep(tcg_env, tcg_constant_tl(RISCV_EXCP_SW_CHECK_FCFI_TVAL), - tcg_constant_tl(LABEL_MISMATCH_LPAD), tcg_constant_tl(0)); + tcg_constant_tl(LABEL_MISMATCH_LPAD), + tcg_constant_tl(a->imm_cfi20)); gen_set_label(skip); } =20 diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 3b47fb34ea..07990e6589 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -24,6 +24,7 @@ #include "exec/exec-all.h" #include "exec/cpu_ldst.h" #include "exec/helper-proto.h" +#include "trace.h" =20 /* Exceptions processing helpers */ G_NORETURN void riscv_raise_exception(CPURISCVState *env, @@ -262,6 +263,29 @@ void helper_cbo_inval(CPURISCVState *env, target_ulong= address) void helper_raise_sw_check_excep(CPURISCVState *env, target_ulong swcheck_= code, target_ulong arg1, target_ulong arg2) { + switch (swcheck_code) { + case RISCV_EXCP_SW_CHECK_FCFI_TVAL: + switch (arg1) { + case MISSING_LPAD: + trace_zicfilp_missing_lpad_instr(arg2); + break; + case MISALIGNED_LPAD: + trace_zicfilp_unaligned_lpad_instr(arg2); + break; + case LABEL_MISMATCH_LPAD: + trace_zicfilp_lpad_reg_mismatch(arg2); + break; + } + break; + case RISCV_EXCP_SW_CHECK_BCFI_TVAL: + trace_zicfiss_sspopchk_reg_mismatch(arg1, arg2); + break; + default: + /* any other value of swcheck_code is asserted */ + assert(swcheck_code || (swcheck_code =3D=3D 0)); + break; + } + env->sw_check_code =3D swcheck_code; riscv_raise_exception(env, RISCV_EXCP_SW_CHECK, GETPC()); } diff --git a/target/riscv/trace-events b/target/riscv/trace-events index 49ec4d3b7d..0e8807f0d4 100644 --- a/target/riscv/trace-events +++ b/target/riscv/trace-events @@ -9,3 +9,9 @@ pmpaddr_csr_write(uint64_t mhartid, uint32_t addr_index, ui= nt64_t val) "hart %" =20 mseccfg_csr_read(uint64_t mhartid, uint64_t val) "hart %" PRIu64 ": read m= seccfg, val: 0x%" PRIx64 mseccfg_csr_write(uint64_t mhartid, uint64_t val) "hart %" PRIu64 ": write= mseccfg, val: 0x%" PRIx64 + +# zicfiss/lp +zicfiss_sspopchk_reg_mismatch(uint64_t ssra, uint64_t rs1) "shadow_stack_r= a: 0x%" PRIx64 ", rs1: 0x%" PRIx64 +zicfilp_missing_lpad_instr(uint64_t pc_first) "pc_first: 0x%" PRIx64 +zicfilp_unaligned_lpad_instr(uint64_t pc_next) "pc_next: 0x%" PRIx64 +zicfilp_lpad_reg_mismatch(int lpad_label) "lpad_label: 0x%x" diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 4772191bd8..9ef1f220e0 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1302,7 +1302,7 @@ static void riscv_tr_tb_start(DisasContextBase *db, C= PUState *cpu) tcg_gen_brcondi_i32(TCG_COND_EQ, immediate, 0, l); gen_helper_raise_sw_check_excep(tcg_env, tcg_constant_tl(RISCV_EXCP_SW_CHECK_FCFI_TVAL), - tcg_constant_tl(MISSING_LPAD), tcg_constant_tl(0)); + tcg_constant_tl(MISSING_LPAD), tcg_constant_tl(ctx->base.pc_fi= rst)); gen_set_label(l); /* * Despite the use of gen_exception_illegal(), the rest of --=20 2.44.0