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Tue, 06 Aug 2024 17:07:14 -0700 (PDT) From: Deepak Gupta To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: richard.henderson@linaro.org, pbonzini@redhat.com, palmer@dabbelt.com, Alistair.Francis@wdc.com, laurent@vivier.eu, bmeng.cn@gmail.com, liwei1518@gmail.com, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, Deepak Gupta Subject: [PATCH v3 15/20] target/riscv: shadow stack mmu index for shadow stack instructions Date: Tue, 6 Aug 2024 17:06:46 -0700 Message-ID: <20240807000652.1417776-16-debug@rivosinc.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: <20240807000652.1417776-1-debug@rivosinc.com> References: <20240807000652.1417776-1-debug@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=debug@rivosinc.com; helo=mail-pl1-x629.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @rivosinc-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1722989497702116600 Content-Type: text/plain; charset="utf-8" Shadow stack instructions shadow stack mmu index for load/stores. `MMU_IDX_SS_ACCESS` at bit positon 3 is used as shadow stack index. Shadow stack mmu index depend on privilege and SUM bit. If shadow stack accesses happening in user mode, shadow stack mmu index =3D 0b1000. If shaodw stack access happening in supervisor mode mmu index =3D 0b1001. If shadow stack access happening in supervisor mode with SUM=3D1 then mmu index =3D 0b1010 Signed-off-by: Deepak Gupta --- target/riscv/cpu.h | 13 ++++++++++ target/riscv/cpu_helper.c | 3 +++ target/riscv/insn_trans/trans_rva.c.inc | 8 ++++++ target/riscv/insn_trans/trans_rvzicfiss.c.inc | 6 +++++ target/riscv/internals.h | 1 + target/riscv/translate.c | 25 +++++++++++++++++++ 6 files changed, 56 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 6da94c417c..3ad220a9fe 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -615,6 +615,19 @@ FIELD(TB_FLAGS, FCFI_ENABLED, 28, 1) FIELD(TB_FLAGS, FCFI_LP_EXPECTED, 29, 1) /* zicfiss needs a TB flag so that correct TB is located based on tb flags= */ FIELD(TB_FLAGS, BCFI_ENABLED, 30, 1) +/* + * zicfiss shadow stack is special memory on which regular stores aren't + * allowed but shadow stack stores are allowed. Shadow stack stores can + * happen as `sspush` or `ssamoswap` instructions. `sspush` implicitly + * takes shadow stack address from CSR_SSP. But `ssamoswap` takes address + * from encoded input register and it will be used by supervisor software + * to access (read/write) user shadow stack for setting up rt_frame during + * signal delivery. Supervisor software will do so by setting SUM=3D1. Thus + * a TB flag is needed if SUM was 1 during TB generation to correctly + * reflect memory permissions to access shadow stack user memory from + * supervisor mode. + */ +FIELD(TB_FLAGS, SUM, 31, 1) =20 #ifdef TARGET_RISCV32 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 5d5da8dce1..ad40b10e74 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -181,6 +181,9 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc, fs =3D EXT_STATUS_DIRTY; vs =3D EXT_STATUS_DIRTY; #else + flags =3D FIELD_DP32(flags, TB_FLAGS, SUM, + ((env->mstatus & MSTATUS_SUM) =3D=3D MSTATUS_SUM)); + flags =3D FIELD_DP32(flags, TB_FLAGS, PRIV, env->priv); =20 flags |=3D riscv_env_mmu_index(env, 0); diff --git a/target/riscv/insn_trans/trans_rva.c.inc b/target/riscv/insn_tr= ans/trans_rva.c.inc index db6c03f6a8..68b71339a3 100644 --- a/target/riscv/insn_trans/trans_rva.c.inc +++ b/target/riscv/insn_trans/trans_rva.c.inc @@ -132,6 +132,10 @@ static bool trans_ssamoswap_w(DisasContext *ctx, arg_a= moswap_w *a) =20 decode_save_opc(ctx); src1 =3D get_address(ctx, a->rs1, 0); +#ifndef CONFIG_USER_ONLY + /* Shadow stack access and thus index is SS TLB index */ + ss_mmu_idx =3D get_ss_index(ctx); +#endif =20 tcg_gen_atomic_xchg_tl(dest, src1, src2, ss_mmu_idx, (MO_ALIGN | MO_TE= SL)); gen_set_gpr(ctx, a->rd, dest); @@ -224,6 +228,10 @@ static bool trans_ssamoswap_d(DisasContext *ctx, arg_a= moswap_w *a) =20 decode_save_opc(ctx); src1 =3D get_address(ctx, a->rs1, 0); +#ifndef CONFIG_USER_ONLY + /* Shadow stack access and thus index is SS TLB index */ + ss_mmu_idx =3D get_ss_index(ctx); +#endif =20 tcg_gen_atomic_xchg_tl(dest, src1, src2, ss_mmu_idx, (MO_ALIGN | MO_TE= SQ)); gen_set_gpr(ctx, a->rd, dest); diff --git a/target/riscv/insn_trans/trans_rvzicfiss.c.inc b/target/riscv/i= nsn_trans/trans_rvzicfiss.c.inc index c538b7ad99..4e741c061d 100644 --- a/target/riscv/insn_trans/trans_rvzicfiss.c.inc +++ b/target/riscv/insn_trans/trans_rvzicfiss.c.inc @@ -70,6 +70,9 @@ static bool trans_sspopchk(DisasContext *ctx, arg_sspopch= k *a) TCGv_i32 ssp_csr =3D tcg_constant_i32(CSR_SSP); TCGv data =3D tcg_temp_new(); gen_helper_csrr(addr, tcg_env, ssp_csr); +#ifndef CONFIG_USER_ONLY + ss_mmu_idx =3D get_ss_index(ctx); +#endif =20 tcg_gen_qemu_ld_tl(data, addr, ss_mmu_idx, mxl_memop(ctx) | MO_ALIGN); @@ -118,6 +121,9 @@ static bool trans_sspush(DisasContext *ctx, arg_sspush = *a) TCGv_i32 ssp_csr =3D tcg_constant_i32(CSR_SSP); TCGv data =3D get_gpr(ctx, a->rs2, EXT_NONE); gen_helper_csrr(addr, tcg_env, ssp_csr); +#ifndef CONFIG_USER_ONLY + ss_mmu_idx =3D get_ss_index(ctx); +#endif =20 tcg_gen_addi_tl(addr, addr, tmp); =20 diff --git a/target/riscv/internals.h b/target/riscv/internals.h index dad0657c80..5147d6bf90 100644 --- a/target/riscv/internals.h +++ b/target/riscv/internals.h @@ -32,6 +32,7 @@ * - S+SUM+2STAGE 0b110 * - Shadow stack+U 0b1000 * - Shadow stack+S 0b1001 + * - Shadow stack+SUM 0b1010 */ #define MMUIdx_U 0 #define MMUIdx_S 1 diff --git a/target/riscv/translate.c b/target/riscv/translate.c index de375c32a1..4772191bd8 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -122,6 +122,8 @@ typedef struct DisasContext { bool fcfi_lp_expected; /* zicfiss extension, if shadow stack was enabled during TB gen */ bool bcfi_enabled; + /* SUM was on during tb translation? */ + bool sum; } DisasContext; =20 static inline bool has_ext(DisasContext *ctx, uint32_t ext) @@ -1127,6 +1129,29 @@ static uint32_t opcode_at(DisasContextBase *dcbase, = target_ulong pc) return translator_ldl(env, &ctx->base, pc); } =20 +#ifndef CONFIG_USER_ONLY +static unsigned int get_ss_index(DisasContext *ctx) +{ + int ss_mmu_idx =3D MMU_IDX_SS_ACCESS; + + /* + * If priv mode is S then a separate index for supervisor + * shadow stack accesses + */ + if (ctx->priv =3D=3D PRV_S) { + ss_mmu_idx |=3D MMUIdx_S; + } + + /* If SUM was set, SS index should have S cleared */ + if (ctx->sum) { + ss_mmu_idx &=3D ~(MMUIdx_S); + ss_mmu_idx |=3D MMUIdx_S_SUM; + } + + return ss_mmu_idx; +} +#endif + /* Include insn module translation function */ #include "insn_trans/trans_rvi.c.inc" #include "insn_trans/trans_rvm.c.inc" --=20 2.44.0