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[176.184.30.206]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a7dc9e83eccsm543566666b.184.2024.08.06.05.52.54 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 06 Aug 2024 05:52:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1722948776; x=1723553576; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Pc4HRKn0ABU9Etyo/i6+qtUkhxyrZpQEkVJjk1kRbzM=; b=zGVH41lOfI9QobnLVPP3IKg1NYgCrWieIp1p3WUTV+RpcWc23XXHBfQe5+VMpMPUEE yufuoKP5ENFt5lTxe2FrRLNOtcrGgjJJXvZ4keeZi1/IiSa0fEHsdOkAs0k4sIhmFkmm cJJnBKDvTce82KL0gf4+9F7uDRQS/gHL0i8cyZ5KQ4GpAuK1jx4uisMPCDZP1/MJ/nDD LSVQ2DiLP9/Yzy+V7w/1QCOx9ubQQfUhbz4oldB2eSDlWoO50uynR16CXkAssPIQY3hr Zy0yL5JGhnHc9WMoqwtEa8FC599cadtyt4QiTTf304j78t2LzhPDOidCSEofP0mdU8qn wiaA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1722948776; x=1723553576; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Pc4HRKn0ABU9Etyo/i6+qtUkhxyrZpQEkVJjk1kRbzM=; b=ewmZ/2qylKEBxE9AqYJZx/jwuQ+5AYw1E7+A9dHKunHRgMYyeEKZyY/2zBXGzKV71E 1F8LCrWw5ZW3KexblnmxfFTjvgg59G3WcQMZfgO/2GZVoPnvig/rw5mRCMfMA4N8V2Pe 9O3NAg3HWb8h+j51LtlJ38aDRD4MQLS5s2xXpk63G+zv7TEkcnKaJDNeXYMGF5S5Wthl IrKy7neFGS4e4P9pkGYXn1yMcwXle2whyQUD8YMRwTKvLoEuHKZYYRRY3ATSsge4YSQH NZgzQpZbmSMU+pEIkIMErP57LCTtJ5pJ2bvE4x2ic8yuWz24mJbD9XDGaqQMCafkU7V/ YaiQ== X-Gm-Message-State: AOJu0YzFzSvwW8cNyf0SvMOSRNK+3vKB9R2T5PfN8lkNaKpZf4BC9cP7 vRNQKXTlqYBCFW6KIyGvK/cVqsdBci6YJm83IhUkDPV+fADisdTGNMvVhEh6RVNgwNCq3h8Elru X X-Google-Smtp-Source: AGHT+IHzurmqcC2QcHCIcRuCYYdVCMIOyDluRId6nd/vITV2mzh8vtkWBTQ8HHIpwE57+Phc+89LPg== X-Received: by 2002:a05:6512:1051:b0:51a:f689:b4df with SMTP id 2adb3069b0e04-530bb39b06cmr11086986e87.44.1722948776211; Tue, 06 Aug 2024 05:52:56 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Bibo Mao , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Song Gao , Richard Henderson , Jiaxun Yang Subject: [PULL 09/28] hw/intc/loongson_ipi: Add LoongsonIPICommonClass::cpu_by_arch_id handler Date: Tue, 6 Aug 2024 14:51:37 +0200 Message-ID: <20240806125157.91185-10-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240806125157.91185-1-philmd@linaro.org> References: <20240806125157.91185-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::235; envelope-from=philmd@linaro.org; helo=mail-lj1-x235.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1722948819580116600 From: Bibo Mao Allow Loongson IPI implementations to have their own cpu_by_arch_id() handler. Signed-off-by: Bibo Mao [PMD: Extracted from bigger commit, added commit description] Co-Developed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Bibo Mao Tested-by: Bibo Mao Acked-by: Song Gao Reviewed-by: Richard Henderson Reviewed-by: Jiaxun Yang Tested-by: Jiaxun Yang Message-Id: <20240805180622.21001-10-philmd@linaro.org> --- include/hw/intc/loongson_ipi_common.h | 1 + hw/intc/loongson_ipi.c | 10 +++++++--- 2 files changed, 8 insertions(+), 3 deletions(-) diff --git a/include/hw/intc/loongson_ipi_common.h b/include/hw/intc/loongs= on_ipi_common.h index 1a2ee41cc9..8997676f0d 100644 --- a/include/hw/intc/loongson_ipi_common.h +++ b/include/hw/intc/loongson_ipi_common.h @@ -41,6 +41,7 @@ struct LoongsonIPICommonClass { SysBusDeviceClass parent_class; =20 AddressSpace *(*get_iocsr_as)(CPUState *cpu); + CPUState *(*cpu_by_arch_id)(int64_t id); }; =20 /* Mainy used by iocsr read and write */ diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c index eb99de9068..4a8e743528 100644 --- a/hw/intc/loongson_ipi.c +++ b/hw/intc/loongson_ipi.c @@ -128,12 +128,13 @@ static MemTxResult send_ipi_data(LoongsonIPICommonSta= te *ipi, CPUState *cpu, static MemTxResult mail_send(LoongsonIPICommonState *ipi, uint64_t val, MemTxAttrs attrs) { + LoongsonIPICommonClass *licc =3D LOONGSON_IPI_COMMON_GET_CLASS(ipi); uint32_t cpuid; hwaddr addr; CPUState *cs; =20 cpuid =3D extract32(val, 16, 10); - cs =3D cpu_by_arch_id(cpuid); + cs =3D licc->cpu_by_arch_id(cpuid); if (cs =3D=3D NULL) { return MEMTX_DECODE_ERROR; } @@ -147,12 +148,13 @@ static MemTxResult mail_send(LoongsonIPICommonState *= ipi, static MemTxResult any_send(LoongsonIPICommonState *ipi, uint64_t val, MemTxAttrs attrs) { + LoongsonIPICommonClass *licc =3D LOONGSON_IPI_COMMON_GET_CLASS(ipi); uint32_t cpuid; hwaddr addr; CPUState *cs; =20 cpuid =3D extract32(val, 16, 10); - cs =3D cpu_by_arch_id(cpuid); + cs =3D licc->cpu_by_arch_id(cpuid); if (cs =3D=3D NULL) { return MEMTX_DECODE_ERROR; } @@ -169,6 +171,7 @@ static MemTxResult loongson_ipi_core_writel(void *opaqu= e, hwaddr addr, { IPICore *s =3D opaque; LoongsonIPICommonState *ipi =3D s->ipi; + LoongsonIPICommonClass *licc =3D LOONGSON_IPI_COMMON_GET_CLASS(ipi); int index =3D 0; uint32_t cpuid; uint8_t vector; @@ -203,7 +206,7 @@ static MemTxResult loongson_ipi_core_writel(void *opaqu= e, hwaddr addr, cpuid =3D extract32(val, 16, 10); /* IPI status vector */ vector =3D extract8(val, 0, 5); - cs =3D cpu_by_arch_id(cpuid); + cs =3D licc->cpu_by_arch_id(cpuid); if (cs =3D=3D NULL || cs->cpu_index >=3D ipi->num_cpu) { return MEMTX_DECODE_ERROR; } @@ -367,6 +370,7 @@ static void loongson_ipi_class_init(ObjectClass *klass,= void *data) device_class_set_parent_unrealize(dc, loongson_ipi_unrealize, &lic->parent_unrealize); licc->get_iocsr_as =3D get_iocsr_as; + licc->cpu_by_arch_id =3D cpu_by_arch_id; } =20 static const TypeInfo loongson_ipi_types[] =3D { --=20 2.45.2