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([203.56.128.103]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7106ed16cb3sm4576038b3a.179.2024.08.04.17.31.39 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 04 Aug 2024 17:31:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1722817902; x=1723422702; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=2FAvv3yZjIy3oYnoHY2EdlCQMFjiKoZMDRTSrJ4FWdU=; b=DGw77imu05A8s3Wm9ChBRvPP2bHqXr9CRSXCth994kMQ6p4uuyhnOALg4HgcBTgBe8 wYf8ej5gjLQ8pfA7js+SDHnkDxaeNVjiNOIFOKmolqbYzIr0N87JVnB/t7PH7hJUFUvh 7sc+xsQc0w3ssfyVuGqR/ckDcnDZzytnmk/dR+2DAzVDii+stZyLsXFM7xQvaWBc7ZVU QHgZ6iCvH7ikhUNrn2ilOyhBKa4O5p7MszRFm0HWuQHPcXhmW76Tc3OIne1A0KyHqp06 QUbszlhOB+nBeydCW5KBFkY1sfuZoKtrmuIHauVLA3yB6WlV9g89n+ZQEIeNrglL2RNR U0lw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1722817902; x=1723422702; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2FAvv3yZjIy3oYnoHY2EdlCQMFjiKoZMDRTSrJ4FWdU=; b=oioJ6C3VZo6iWLkNEDNMJ625EOnaxpoyAmBElnm4RT7vzoNyMwj9CXHlY98WNxLY+/ HlAtLKaAZ5IJp6I72kVMUJcM6XGyvkSDnfFPTxGhIr0yltsDRaRowuFDysmElTcxu4pT XHN9CuAOB8eeZOIm2ul3YHnl6C74swy/54evTjYYOjfIg2MhmxEBzGeA81W9/dJqPlbt bE77cOLIjjcQ8wmPWO9ci2FAiCzDNopsZykf6C9s9Qv0XhIqEsn8Qv1x/ckaAfQvH6gw UbwPI9iyl4ZQVcQ0p6M8suX0P2X4E/8PUnJr+Ta6A299lvIhXX2SBqvOgzbR5kzDa6zE UoBQ== X-Gm-Message-State: AOJu0Yz672P3R8TBkR58JIVS+DQaU8cSlMvn6qOhrnP7nLqz/eoER3sZ EhOJlcIz39j54m2xR+RrIEzd8RX7E0nAfI4v94EUSBjcppjnGgQ7E0L50aAtJwfr7RViXCH+9Vk PKkm+yw== X-Google-Smtp-Source: AGHT+IFaTP8oCUyXymoIl3zTm62gsDOW4sU49if+syXviCtCfc9ZQ/LZi+pDCHnf+Uw4SQP9eQ7Sgw== X-Received: by 2002:a05:6a00:1407:b0:70d:3a45:5b44 with SMTP id d2e1a72fcca58-7106cfccce4mr13703097b3a.14.1722817901440; Sun, 04 Aug 2024 17:31:41 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH for-9.1] target/i386: Fix VSIB decode Date: Mon, 5 Aug 2024 10:31:24 +1000 Message-ID: <20240805003130.1421051-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240805003130.1421051-1-richard.henderson@linaro.org> References: <20240805003130.1421051-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1722817955534116600 Content-Type: text/plain; charset="utf-8" With normal SIB, index =3D=3D 4 indicates no index. With VSIB, there is no exception for VR4/VR12. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2474 Signed-off-by: Richard Henderson --- target/i386/tcg/translate.c | 20 ++++++++++---------- target/i386/tcg/decode-new.c.inc | 3 ++- 2 files changed, 12 insertions(+), 11 deletions(-) diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index fb0d01b356..98f5fe61ed 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -1534,7 +1534,7 @@ typedef struct AddressParts { } AddressParts; =20 static AddressParts gen_lea_modrm_0(CPUX86State *env, DisasContext *s, - int modrm) + int modrm, bool is_vsib) { int def_seg, base, index, scale, mod, rm; target_long disp; @@ -1563,7 +1563,7 @@ static AddressParts gen_lea_modrm_0(CPUX86State *env,= DisasContext *s, int code =3D x86_ldub_code(env, s); scale =3D (code >> 6) & 3; index =3D ((code >> 3) & 7) | REX_X(s); - if (index =3D=3D 4) { + if (index =3D=3D 4 && !is_vsib) { index =3D -1; /* no index */ } base =3D (code & 7) | REX_B(s); @@ -1693,21 +1693,21 @@ static TCGv gen_lea_modrm_1(DisasContext *s, Addres= sParts a, bool is_vsib) =20 static void gen_lea_modrm(CPUX86State *env, DisasContext *s, int modrm) { - AddressParts a =3D gen_lea_modrm_0(env, s, modrm); + AddressParts a =3D gen_lea_modrm_0(env, s, modrm, false); TCGv ea =3D gen_lea_modrm_1(s, a, false); gen_lea_v_seg(s, ea, a.def_seg, s->override); } =20 static void gen_nop_modrm(CPUX86State *env, DisasContext *s, int modrm) { - (void)gen_lea_modrm_0(env, s, modrm); + (void)gen_lea_modrm_0(env, s, modrm, false); } =20 /* Used for BNDCL, BNDCU, BNDCN. */ static void gen_bndck(CPUX86State *env, DisasContext *s, int modrm, TCGCond cond, TCGv_i64 bndv) { - AddressParts a =3D gen_lea_modrm_0(env, s, modrm); + AddressParts a =3D gen_lea_modrm_0(env, s, modrm, false); TCGv ea =3D gen_lea_modrm_1(s, a, false); =20 tcg_gen_extu_tl_i64(s->tmp1_i64, ea); @@ -2428,7 +2428,7 @@ static bool disas_insn_x87(DisasContext *s, CPUState = *cpu, int b) op =3D ((b & 7) << 3) | ((modrm >> 3) & 7); if (mod !=3D 3) { /* memory op */ - AddressParts a =3D gen_lea_modrm_0(env, s, modrm); + AddressParts a =3D gen_lea_modrm_0(env, s, modrm, false); TCGv ea =3D gen_lea_modrm_1(s, a, false); TCGv last_addr =3D tcg_temp_new(); bool update_fdp =3D true; @@ -3089,7 +3089,7 @@ static void disas_insn_old(DisasContext *s, CPUState = *cpu, int b) rm =3D (modrm & 7) | REX_B(s); gen_op_mov_v_reg(s, MO_32, s->T1, reg); if (mod !=3D 3) { - AddressParts a =3D gen_lea_modrm_0(env, s, modrm); + AddressParts a =3D gen_lea_modrm_0(env, s, modrm, false); /* specific case: we need to add a displacement */ gen_exts(ot, s->T1); tcg_gen_sari_tl(s->tmp0, s->T1, 3 + ot); @@ -3646,7 +3646,7 @@ static void disas_insn_old(DisasContext *s, CPUState = *cpu, int b) } } else if (mod !=3D 3) { /* bndldx */ - AddressParts a =3D gen_lea_modrm_0(env, s, modrm); + AddressParts a =3D gen_lea_modrm_0(env, s, modrm, false); if (reg >=3D 4 || (prefixes & PREFIX_LOCK) || s->aflag =3D=3D MO_16 @@ -3690,7 +3690,7 @@ static void disas_insn_old(DisasContext *s, CPUState = *cpu, int b) || s->aflag =3D=3D MO_16) { goto illegal_op; } - AddressParts a =3D gen_lea_modrm_0(env, s, modrm); + AddressParts a =3D gen_lea_modrm_0(env, s, modrm, false); if (a.base >=3D 0) { tcg_gen_extu_tl_i64(cpu_bndl[reg], cpu_regs[a.base]); if (!CODE64(s)) { @@ -3751,7 +3751,7 @@ static void disas_insn_old(DisasContext *s, CPUState = *cpu, int b) } } else if (mod !=3D 3) { /* bndstx */ - AddressParts a =3D gen_lea_modrm_0(env, s, modrm); + AddressParts a =3D gen_lea_modrm_0(env, s, modrm, false); if (reg >=3D 4 || (prefixes & PREFIX_LOCK) || s->aflag =3D=3D MO_16 diff --git a/target/i386/tcg/decode-new.c.inc b/target/i386/tcg/decode-new.= c.inc index d2da1d396d..b22210f45d 100644 --- a/target/i386/tcg/decode-new.c.inc +++ b/target/i386/tcg/decode-new.c.inc @@ -1811,7 +1811,8 @@ static int decode_modrm(DisasContext *s, CPUX86State = *env, X86DecodedInsn *decod } else { op->has_ea =3D true; op->n =3D -1; - decode->mem =3D gen_lea_modrm_0(env, s, get_modrm(s, env)); + decode->mem =3D gen_lea_modrm_0(env, s, modrm, + decode->e.vex_class =3D=3D 12); } return modrm; } --=20 2.43.0