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charset="utf-8" Compressed encodings also applies to zama16b. https://github.com/riscv/riscv-isa-manual/pull/1557 Suggested-by: Alistair Francis Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/insn_trans/trans_rvd.c.inc | 4 ++-- target/riscv/insn_trans/trans_rvf.c.inc | 4 ++-- target/riscv/insn_trans/trans_rvi.c.inc | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvd.c.inc b/target/riscv/insn_tr= ans/trans_rvd.c.inc index 1f5fac65a2..0ac42c3223 100644 --- a/target/riscv/insn_trans/trans_rvd.c.inc +++ b/target/riscv/insn_trans/trans_rvd.c.inc @@ -47,7 +47,7 @@ static bool trans_fld(DisasContext *ctx, arg_fld *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVD); =20 - if (ctx->cfg_ptr->ext_zama16b && (ctx->cur_insn_len !=3D 2)) { + if (ctx->cfg_ptr->ext_zama16b) { memop |=3D MO_ATOM_WITHIN16; } =20 @@ -67,7 +67,7 @@ static bool trans_fsd(DisasContext *ctx, arg_fsd *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVD); =20 - if (ctx->cfg_ptr->ext_zama16b && (ctx->cur_insn_len !=3D 2)) { + if (ctx->cfg_ptr->ext_zama16b) { memop |=3D MO_ATOM_WITHIN16; } =20 diff --git a/target/riscv/insn_trans/trans_rvf.c.inc b/target/riscv/insn_tr= ans/trans_rvf.c.inc index f771aa1939..0222a728df 100644 --- a/target/riscv/insn_trans/trans_rvf.c.inc +++ b/target/riscv/insn_trans/trans_rvf.c.inc @@ -48,7 +48,7 @@ static bool trans_flw(DisasContext *ctx, arg_flw *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); =20 - if (ctx->cfg_ptr->ext_zama16b && (ctx->cur_insn_len !=3D 2)) { + if (ctx->cfg_ptr->ext_zama16b) { memop |=3D MO_ATOM_WITHIN16; } =20 @@ -70,7 +70,7 @@ static bool trans_fsw(DisasContext *ctx, arg_fsw *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); =20 - if (ctx->cfg_ptr->ext_zama16b && (ctx->cur_insn_len !=3D 2)) { + if (ctx->cfg_ptr->ext_zama16b) { memop |=3D MO_ATOM_WITHIN16; } =20 diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_tr= ans/trans_rvi.c.inc index 98e3806d5e..fab5c06719 100644 --- a/target/riscv/insn_trans/trans_rvi.c.inc +++ b/target/riscv/insn_trans/trans_rvi.c.inc @@ -268,7 +268,7 @@ static bool gen_load(DisasContext *ctx, arg_lb *a, MemO= p memop) { bool out; =20 - if (ctx->cfg_ptr->ext_zama16b && (ctx->cur_insn_len !=3D 2)) { + if (ctx->cfg_ptr->ext_zama16b) { memop |=3D MO_ATOM_WITHIN16; } decode_save_opc(ctx); @@ -369,7 +369,7 @@ static bool gen_store_i128(DisasContext *ctx, arg_sb *a= , MemOp memop) =20 static bool gen_store(DisasContext *ctx, arg_sb *a, MemOp memop) { - if (ctx->cfg_ptr->ext_zama16b && (ctx->cur_insn_len !=3D 2)) { + if (ctx->cfg_ptr->ext_zama16b) { memop |=3D MO_ATOM_WITHIN16; } decode_save_opc(ctx); --=20 2.25.1 From nobody Sun Nov 24 14:31:06 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.alibaba.com ARC-Seal: i=1; a=rsa-sha256; t=1722583597; cv=none; d=zohomail.com; s=zohoarc; b=OZYOTn4EFc2Fq57M8Qa4LWIsxR9Qpi26UyXoAU6iZWpbBfyl5DqAHlTKDd1iFIEdgoLKVsegHyhluixuEtZ3LJsBoCd+xPOhC1U0sjPHrGqrfy4d/ZisyDc1eoDY1T0CmgR8nx1UFrP5I0zV3cOifmb5rxCdN3eQwsiyVY8WNWE= ARC-Message-Signature: i=1; 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charset="utf-8" Zama16b loads and stores of no more than MXLEN bits defined in the F, D, an= d Q extensions. Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/insn_trans/trans_rvd.c.inc | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvd.c.inc b/target/riscv/insn_tr= ans/trans_rvd.c.inc index 0ac42c3223..49682292b8 100644 --- a/target/riscv/insn_trans/trans_rvd.c.inc +++ b/target/riscv/insn_trans/trans_rvd.c.inc @@ -47,7 +47,11 @@ static bool trans_fld(DisasContext *ctx, arg_fld *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVD); =20 - if (ctx->cfg_ptr->ext_zama16b) { + /* + * Zama16b applies to loads and stores of no more than MXLEN bits defi= ned + * in the F, D, and Q extensions. + */ + if ((get_xl_max(ctx) >=3D MXL_RV64) && ctx->cfg_ptr->ext_zama16b) { memop |=3D MO_ATOM_WITHIN16; } =20 @@ -67,7 +71,7 @@ static bool trans_fsd(DisasContext *ctx, arg_fsd *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVD); =20 - if (ctx->cfg_ptr->ext_zama16b) { + if ((get_xl_max(ctx) >=3D MXL_RV64) && ctx->cfg_ptr->ext_zama16b) { memop |=3D MO_ATOM_WITHIN16; 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Fri, 02 Aug 2024 15:26:34 +0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1722583594; h=From:To:Subject:Date:Message-Id:MIME-Version:Content-Type; bh=xlzdiXK8B41IrEGqINwACSXTyo01TRzc8KDruDLPmlI=; b=lZ3cxdm3OTbX37KKEKGyYs1A1xB57WvHXRR7X39vf7rSR3glI2TCCxw+Ioeh+iA8mWxp5WYnkQ/f78ZIWhoXwac/mAmItet3Mr4s1L96nU0aAr65hQUgPbgsY22MfUbQ8qMBVM86RHr8WCCUhyCygGl0Rwk/YAPCWiDxv9rP1PI= X-Alimail-AntiSpam: AC=PASS; BC=-1|-1; BR=01201311R171e4; CH=green; DM=||false|; DS=||; FP=0|-1|-1|-1|0|-1|-1|-1; HT=maildocker-contentspam033037067112; MF=zhiwei_liu@linux.alibaba.com; NM=1; PH=DS; RN=9; SR=0; TI=SMTPD_---0WBwhJWB_1722583592; From: LIU Zhiwei To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, palmer@dabbelt.com, alistair.francis@wdc.com, dbarboza@ventanamicro.com, liwei1518@gmail.com, bmeng.cn@gmail.com, zhiwei_liu@linux.alibaba.com, richard.henderson@linaro.org Subject: [PATCH v3 3/3] target/riscv: Relax fld alignment requirement Date: Fri, 2 Aug 2024 15:24:17 +0800 Message-Id: <20240802072417.659-4-zhiwei_liu@linux.alibaba.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20240802072417.659-1-zhiwei_liu@linux.alibaba.com> References: <20240802072417.659-1-zhiwei_liu@linux.alibaba.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=115.124.30.111; envelope-from=zhiwei_liu@linux.alibaba.com; helo=out30-111.freemail.mail.aliyun.com X-Spam_score_int: -174 X-Spam_score: -17.5 X-Spam_bar: ----------------- X-Spam_report: (-17.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, ENV_AND_HDR_SPF_MATCH=-0.5, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, UNPARSEABLE_RELAY=0.001, USER_IN_DEF_DKIM_WL=-7.5, USER_IN_DEF_SPF_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linux.alibaba.com) X-ZM-MESSAGEID: 1722583628076116600 According to the risc-v specification: "FLD and FSD are only guaranteed to execute atomically if the effective address is naturally aligned and XLEN=E2=89=A564." We currently implement fld as MO_ATOM_IFALIGN when XLEN < 64, which does not violate the rules. But it will hide some problems. So relax it to MO_ATOM_NONE. Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/insn_trans/trans_rvd.c.inc | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvd.c.inc b/target/riscv/insn_tr= ans/trans_rvd.c.inc index 49682292b8..8a46124f98 100644 --- a/target/riscv/insn_trans/trans_rvd.c.inc +++ b/target/riscv/insn_trans/trans_rvd.c.inc @@ -48,11 +48,17 @@ static bool trans_fld(DisasContext *ctx, arg_fld *a) REQUIRE_EXT(ctx, RVD); =20 /* - * Zama16b applies to loads and stores of no more than MXLEN bits defi= ned - * in the F, D, and Q extensions. + * FLD and FSD are only guaranteed to execute atomically if the effect= ive + * address is naturally aligned and XLEN=E2=89=A564. Also, zama16b app= lies to + * loads and stores of no more than MXLEN bits defined in the F, D, and + * Q extensions. */ - if ((get_xl_max(ctx) >=3D MXL_RV64) && ctx->cfg_ptr->ext_zama16b) { + if (get_xl_max(ctx) =3D=3D MXL_RV32) { + memop |=3D MO_ATOM_NONE; + } else if (ctx->cfg_ptr->ext_zama16b) { memop |=3D MO_ATOM_WITHIN16; + } else { + memop |=3D MO_ATOM_IFALIGN; } =20 decode_save_opc(ctx); @@ -71,8 +77,12 @@ static bool trans_fsd(DisasContext *ctx, arg_fsd *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVD); =20 - if ((get_xl_max(ctx) >=3D MXL_RV64) && ctx->cfg_ptr->ext_zama16b) { + if (get_xl_max(ctx) =3D=3D MXL_RV32) { + memop |=3D MO_ATOM_NONE; + } else if (ctx->cfg_ptr->ext_zama16b) { memop |=3D MO_ATOM_WITHIN16; + } else { + memop |=3D MO_ATOM_IFALIGN; } =20 decode_save_opc(ctx); --=20 2.25.1