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Fri, 02 Aug 2024 11:16:55 +0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1722568616; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=6qg6J+iIOAJu3sGQvXUBjTvfLvpSIluiwde+u+Oi1AU=; b=ti7JEJgkG+EysvCEQbLcgJmocdyRipIXSAC2Nz/dzUS/i9LJqk/XsYhMQwbEivRsP7l3EHDGFSol/I+ExYjU94VcGxKfUaN/rEyvZKqR+Ip0zzyvUX8lcKV0jnbmWMgAnNyoMWZ8hQ/I/LqifciVpSXlO1m0eNdS9mKe7oYDXUY= X-Alimail-AntiSpam: AC=PASS; BC=-1|-1; BR=01201311R761e4; CH=green; DM=||false|; DS=||; FP=0|-1|-1|-1|0|-1|-1|-1; HT=maildocker-contentspam033037067111; MF=zhiwei_liu@linux.alibaba.com; NM=1; PH=DS; RN=8; SR=0; TI=SMTPD_---0WBvqpPj_1722568615; From: LIU Zhiwei To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, palmer@dabbelt.com, alistair.francis@wdc.com, dbarboza@ventanamicro.com, liwei1518@gmail.com, bmeng.cn@gmail.com, zhiwei_liu@linux.alibaba.com Subject: [PATCH v2 1/3] target/riscv: Remove redundant insn length check for zama16b Date: Fri, 2 Aug 2024 11:16:10 +0800 Message-Id: <20240802031612.604-2-zhiwei_liu@linux.alibaba.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20240802031612.604-1-zhiwei_liu@linux.alibaba.com> References: <20240802031612.604-1-zhiwei_liu@linux.alibaba.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" Compressed encodings also applies to zama16b. https://github.com/riscv/riscv-isa-manual/pull/1557 Suggested-by: Alistair Francis Signed-off-by: LIU Zhiwei --- target/riscv/insn_trans/trans_rvd.c.inc | 9 +++++++-- target/riscv/insn_trans/trans_rvf.c.inc | 4 ++-- target/riscv/insn_trans/trans_rvi.c.inc | 4 ++-- 3 files changed, 11 insertions(+), 6 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvd.c.inc b/target/riscv/insn_tr= ans/trans_rvd.c.inc index 1f5fac65a2..2be037930a 100644 --- a/target/riscv/insn_trans/trans_rvd.c.inc +++ b/target/riscv/insn_trans/trans_rvd.c.inc @@ -47,7 +47,12 @@ static bool trans_fld(DisasContext *ctx, arg_fld *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVD); =20 - if (ctx->cfg_ptr->ext_zama16b && (ctx->cur_insn_len !=3D 2)) { + /* + * Zama16b applies to loads and stores of no more than MXLEN bits defi= ned + * in the F, D, and Q extensions. Otherwise, it falls through to defau= lt + * MO_ATOM_IFALIGN. + */ + if ((ctx->xl >=3D MXL_RV64) && (ctx->cfg_ptr->ext_zama16b)) { memop |=3D MO_ATOM_WITHIN16; } =20 @@ -67,7 +72,7 @@ static bool trans_fsd(DisasContext *ctx, arg_fsd *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVD); =20 - if (ctx->cfg_ptr->ext_zama16b && (ctx->cur_insn_len !=3D 2)) { + if (ctx->cfg_ptr->ext_zama16b) { memop |=3D MO_ATOM_WITHIN16; } =20 diff --git a/target/riscv/insn_trans/trans_rvf.c.inc b/target/riscv/insn_tr= ans/trans_rvf.c.inc index f771aa1939..0222a728df 100644 --- a/target/riscv/insn_trans/trans_rvf.c.inc +++ b/target/riscv/insn_trans/trans_rvf.c.inc @@ -48,7 +48,7 @@ static bool trans_flw(DisasContext *ctx, arg_flw *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); =20 - if (ctx->cfg_ptr->ext_zama16b && (ctx->cur_insn_len !=3D 2)) { + if (ctx->cfg_ptr->ext_zama16b) { memop |=3D MO_ATOM_WITHIN16; } =20 @@ -70,7 +70,7 @@ static bool trans_fsw(DisasContext *ctx, arg_fsw *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); =20 - if (ctx->cfg_ptr->ext_zama16b && (ctx->cur_insn_len !=3D 2)) { + if (ctx->cfg_ptr->ext_zama16b) { memop |=3D MO_ATOM_WITHIN16; } =20 diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_tr= ans/trans_rvi.c.inc index 98e3806d5e..fab5c06719 100644 --- a/target/riscv/insn_trans/trans_rvi.c.inc +++ b/target/riscv/insn_trans/trans_rvi.c.inc @@ -268,7 +268,7 @@ static bool gen_load(DisasContext *ctx, arg_lb *a, MemO= p memop) { bool out; =20 - if (ctx->cfg_ptr->ext_zama16b && (ctx->cur_insn_len !=3D 2)) { + if (ctx->cfg_ptr->ext_zama16b) { memop |=3D MO_ATOM_WITHIN16; } decode_save_opc(ctx); @@ -369,7 +369,7 @@ static bool gen_store_i128(DisasContext *ctx, arg_sb *a= , MemOp memop) =20 static bool gen_store(DisasContext *ctx, arg_sb *a, MemOp memop) { - if (ctx->cfg_ptr->ext_zama16b && (ctx->cur_insn_len !=3D 2)) { + if (ctx->cfg_ptr->ext_zama16b) { memop |=3D MO_ATOM_WITHIN16; } decode_save_opc(ctx); --=20 2.25.1 From nobody Sun Nov 24 14:57:11 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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charset="utf-8" Zama16b loads and stores of no more than MXLEN bits defined in the F, D, an= d Q extensions. Signed-off-by: LIU Zhiwei --- target/riscv/insn_trans/trans_rvd.c.inc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvd.c.inc b/target/riscv/insn_tr= ans/trans_rvd.c.inc index 2be037930a..dbe508c7e0 100644 --- a/target/riscv/insn_trans/trans_rvd.c.inc +++ b/target/riscv/insn_trans/trans_rvd.c.inc @@ -52,7 +52,7 @@ static bool trans_fld(DisasContext *ctx, arg_fld *a) * in the F, D, and Q extensions. Otherwise, it falls through to defau= lt * MO_ATOM_IFALIGN. */ - if ((ctx->xl >=3D MXL_RV64) && (ctx->cfg_ptr->ext_zama16b)) { + if ((ctx->misa_mxl_max >=3D MXL_RV64) && ctx->cfg_ptr->ext_zama16b) { memop |=3D MO_ATOM_WITHIN16; } =20 @@ -72,7 +72,7 @@ static bool trans_fsd(DisasContext *ctx, arg_fsd *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVD); =20 - if (ctx->cfg_ptr->ext_zama16b) { + if ((ctx->misa_mxl_max >=3D MXL_RV64) && ctx->cfg_ptr->ext_zama16b) { memop |=3D MO_ATOM_WITHIN16; } =20 --=20 2.25.1 From nobody Sun Nov 24 14:57:11 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.alibaba.com ARC-Seal: i=1; a=rsa-sha256; t=1722568707; cv=none; d=zohomail.com; s=zohoarc; b=bAg5bXs+NhO3lAZtpCjOyZUUzV61IEMLD5au+8LG9GwNwViZQm2gWHII7EkCYYB0yV0V0h4WLqH09KpRH6m3wsmjJlLlPCUW+C1AhTqdbdHwWNkylYNlQ/4rPqGsZbatJfISDEjrd9TwTHdS/2lctVubNHx8Sy/X1LnHa2Wf6Sw= ARC-Message-Signature: i=1; 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BC=-1|-1; BR=01201311R961e4; CH=green; DM=||false|; DS=||; FP=0|-1|-1|-1|0|-1|-1|-1; HT=maildocker-contentspam033037067112; MF=zhiwei_liu@linux.alibaba.com; NM=1; PH=DS; RN=8; SR=0; TI=SMTPD_---0WBvmM9u_1722568677; From: LIU Zhiwei To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, palmer@dabbelt.com, alistair.francis@wdc.com, dbarboza@ventanamicro.com, liwei1518@gmail.com, bmeng.cn@gmail.com, zhiwei_liu@linux.alibaba.com Subject: [PATCH v2 3/3] target/riscv: Relax fld alignment requirement Date: Fri, 2 Aug 2024 11:16:12 +0800 Message-Id: <20240802031612.604-4-zhiwei_liu@linux.alibaba.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20240802031612.604-1-zhiwei_liu@linux.alibaba.com> References: <20240802031612.604-1-zhiwei_liu@linux.alibaba.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=115.124.30.131; envelope-from=zhiwei_liu@linux.alibaba.com; helo=out30-131.freemail.mail.aliyun.com X-Spam_score_int: -174 X-Spam_score: -17.5 X-Spam_bar: ----------------- X-Spam_report: (-17.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, ENV_AND_HDR_SPF_MATCH=-0.5, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, UNPARSEABLE_RELAY=0.001, USER_IN_DEF_DKIM_WL=-7.5, USER_IN_DEF_SPF_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linux.alibaba.com) X-ZM-MESSAGEID: 1722568708498116600 According to the risc-v specification: "FLD and FSD are only guaranteed to execute atomically if the effective address is naturally aligned and XLEN=E2=89=A564." We currently implement fld as MO_ATOM_IFALIGN when XLEN < 64, which does not violate the rules. But it will hide some problems. So relax it to MO_ATOM_NONE. Signed-off-by: LIU Zhiwei --- target/riscv/insn_trans/trans_rvd.c.inc | 26 ++++++++++++++++++------- 1 file changed, 19 insertions(+), 7 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvd.c.inc b/target/riscv/insn_tr= ans/trans_rvd.c.inc index dbe508c7e0..458d7db745 100644 --- a/target/riscv/insn_trans/trans_rvd.c.inc +++ b/target/riscv/insn_trans/trans_rvd.c.inc @@ -48,12 +48,20 @@ static bool trans_fld(DisasContext *ctx, arg_fld *a) REQUIRE_EXT(ctx, RVD); =20 /* - * Zama16b applies to loads and stores of no more than MXLEN bits defi= ned - * in the F, D, and Q extensions. Otherwise, it falls through to defau= lt - * MO_ATOM_IFALIGN. + * FLD and FSD are only guaranteed to execute atomically if the effect= ive + * address is naturally aligned and XLEN=E2=89=A564. */ - if ((ctx->misa_mxl_max >=3D MXL_RV64) && ctx->cfg_ptr->ext_zama16b) { - memop |=3D MO_ATOM_WITHIN16; + if (ctx->misa_mxl_max >=3D MXL_RV64) { + /* + * Zama16b applies to loads and stores of no more than MXLEN bits + * defined in the F, D, and Q extensions. Otherwise, it falls thro= ugh + * to default MO_ATOM_IFALIGN. + */ + if (ctx->cfg_ptr->ext_zama16b) { + memop |=3D MO_ATOM_WITHIN16; + } + } else { + memop |=3D MO_ATOM_NONE; } =20 decode_save_opc(ctx); @@ -72,8 +80,12 @@ static bool trans_fsd(DisasContext *ctx, arg_fsd *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVD); =20 - if ((ctx->misa_mxl_max >=3D MXL_RV64) && ctx->cfg_ptr->ext_zama16b) { - memop |=3D MO_ATOM_WITHIN16; + if (ctx->misa_mxl_max >=3D MXL_RV64) { + if (ctx->cfg_ptr->ext_zama16b) { + memop |=3D MO_ATOM_WITHIN16; + } + } else { + memop |=3D MO_ATOM_NONE; } =20 decode_save_opc(ctx); --=20 2.25.1