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Thu, 01 Aug 2024 15:03:32 -0700 (PDT) Date: Thu, 1 Aug 2024 15:03:28 -0700 Mime-Version: 1.0 X-Mailer: git-send-email 2.46.0.rc2.264.g509ed76dc8-goog Message-ID: <20240801220328.941866-1-alexrichardson@google.com> Subject: [PATCH] target/arm: add support for 64-bit PMCCNTR in AArch32 mode From: Alex Richardson To: qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: Alex Richardson Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1149; envelope-from=3NAasZg4KCi0JUNgaRLQJaMbXWPXXPUN.LXVZNVd-MNeNUWXWPWd.XaP@flex--alexrichardson.bounces.google.com; helo=mail-yw1-x1149.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Thu, 01 Aug 2024 21:00:22 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @google.com) X-ZM-MESSAGEID: 1722560482937116600 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" See https://developer.arm.com/documentation/ddi0601/2024-06/AArch32-Registe= rs/PMCCNTR--Performance-Monitors-Cycle-Count-Register?lang=3Den Signed-off-by: Alex Richardson --- target/arm/helper.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index 8fb4b474e8..94900667c3 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5952,6 +5952,12 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { .access =3D PL1_RW, .accessfn =3D access_trap_aa32s_el1, .writefn =3D sdcr_write, .fieldoffset =3D offsetoflow32(CPUARMState, cp15.mdcr_el3) }, + { .name =3D "PMCCNTR", .state =3D ARM_CP_STATE_AA32, + .type =3D ARM_CP_ALIAS | ARM_CP_IO | ARM_CP_64BIT, + .cp =3D 15, .crm =3D 9, .opc1 =3D 0, + .access =3D PL0_RW, .resetvalue =3D 0, .fgt =3D FGT_PMCCNTR_EL0, + .readfn =3D pmccntr_read, .writefn =3D pmccntr_write, + .accessfn =3D pmreg_access_ccntr }, }; =20 /* These are present only when EL1 supports AArch32 */ --=20 2.46.0.rc2.264.g509ed76dc8-goog