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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=148.163.158.5; envelope-from=kowal@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1722544358110116600 Content-Type: text/plain; charset="utf-8" From: Glenn Miles Current code was updating the PIPR inside the xive_tctx_accept() function instead of the xive_tctx_set_cppr function, which is where the HW would have it updated. Moved the update to the xive_tctx_set_cppr function which required additional support for pool interrupts. Signed-off-by: Glenn Miles Signed-off-by: Michael Kowal --- hw/intc/xive.c | 34 ++++++++++++++++++++++++++++++++-- 1 file changed, 32 insertions(+), 2 deletions(-) diff --git a/hw/intc/xive.c b/hw/intc/xive.c index 5c4ca7f6e0..d951aac3a0 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -89,7 +89,6 @@ static uint64_t xive_tctx_accept(XiveTCTX *tctx, uint8_t = ring) =20 /* Reset the pending buffer bit */ aregs[TM_IPB] &=3D ~xive_priority_to_ipb(cppr); - regs[TM_PIPR] =3D ipb_to_pipr(aregs[TM_IPB]); =20 /* Drop Exception bit */ regs[TM_NSR] &=3D ~mask; @@ -143,6 +142,8 @@ void xive_tctx_reset_signal(XiveTCTX *tctx, uint8_t rin= g) static void xive_tctx_set_cppr(XiveTCTX *tctx, uint8_t ring, uint8_t cppr) { uint8_t *regs =3D &tctx->regs[ring]; + uint8_t pipr_min; + uint8_t ring_min; =20 trace_xive_tctx_set_cppr(tctx->cs->cpu_index, ring, regs[TM_IPB], regs[TM_PIPR], @@ -154,8 +155,37 @@ static void xive_tctx_set_cppr(XiveTCTX *tctx, uint8_t= ring, uint8_t cppr) =20 tctx->regs[ring + TM_CPPR] =3D cppr; =20 + /* + * Recompute the PIPR based on local pending interrupts. The PHYS + * ring must take the minimum of both the PHYS and POOL PIPR values. + */ + pipr_min =3D ipb_to_pipr(regs[TM_IPB]); + ring_min =3D ring; + + /* PHYS updates also depend on POOL values */ + if (ring =3D=3D TM_QW3_HV_PHYS) { + uint8_t *pregs =3D &tctx->regs[TM_QW2_HV_POOL]; + + /* POOL values only matter if POOL ctx is valid */ + if (pregs[TM_WORD2] & 0x80) { + + uint8_t pool_pipr =3D ipb_to_pipr(pregs[TM_IPB]); + + /* + * Determine highest priority interrupt and + * remember which ring has it. + */ + if (pool_pipr < pipr_min) { + pipr_min =3D pool_pipr; + ring_min =3D TM_QW2_HV_POOL; + } + } + } + + regs[TM_PIPR] =3D pipr_min; + /* CPPR has changed, check if we need to raise a pending exception */ - xive_tctx_notify(tctx, ring); + xive_tctx_notify(tctx, ring_min); } =20 void xive_tctx_ipb_update(XiveTCTX *tctx, uint8_t ring, uint8_t ipb) --=20 2.43.0