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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1fed7cc0213sm142631275ad.72.2024.08.01.07.06.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Aug 2024 07:06:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1722521180; x=1723125980; darn=nongnu.org; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=JXlEGPL9thPPk61Tbq7dliSQC6vKn0rJatKn3l6TSro=; b=PPWARAbuUZEBZIT1KyGVxpWt/bwHyWL/FR0r2iJiXEkZC+jpF48Ca9fanE56EVjSni ZhwW4JGcxGBo3ZJ5c7sxVOh7z0mxCBQyG6sfVXHqVFKRJUfGOuAMButwsAbPz8Lr7ayR JfMWN+Ip/WgtdL2Pp04K/yrTMSFNIq5pDsmurfxWPEgDo4KfMGpt9tYCfeQNoI9y82r6 XIoXe0HgYanxgAwARI6Ka0XYW7IgOQ2cYWTqvwYjvToO+aX4CHcXZJ+yxdComXhQA9y7 ItDHfdruL+6+5YvPr/VpJtU3lbvLDH8c5MWNkkRGeJDw57LTNlWKPta36NjxjvbxMUhT dAUg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1722521180; x=1723125980; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=JXlEGPL9thPPk61Tbq7dliSQC6vKn0rJatKn3l6TSro=; b=h7EIPUQYIrjhprG/m/dGwwSHBhsjKLUKcqJ1xBJ86MKZXBHR1eRx5kOloiNdZS7fFb UZR92Vg4Q5VSBSBzKaTYlOKPg979fpLIJqlHQZhsAchnkFpjC+x3duxsVr+g/RNcj1a/ u8KVNpiCVksi43jHAqB6wrTzrio5S37cwKUq3D8OT+OcgcfaUbrzmPMZWQDKnVKbe2xM hYAEbmyal+VdiQVrzmVrARaagG7AjXBT1HNU2D9IJ6G5GntcOWKA6lIzBlbrTDyY8Bmp NAFegmkx6bPois1Fx2YofZ9iThEcYfNcpnydKuMMpHhlc6ZdK7/vbLnUlLqqwp2sNQ8R yKug== X-Gm-Message-State: AOJu0YxG5eecMfRrP763zGVTZcN4fLqxQeNW8dEUYppD2j3fPTioTNDK /yzGIMRt60K43e0MoCsFpYpYe0Xrnv0egHTnnF+BLPuNpIEr3exMYwSbjoYgTJ/uQby4VsEqYkR XFLY/czqG7yZsMJSfq8SNfibVUed0+qiAYD2H4UAAcXKPs7YR6IRM2SI588/bagYDwHm3oPWMMO Ko6vktAO+V02e5gtq3c13SpW89XiLOXNEt7jd+ X-Google-Smtp-Source: AGHT+IGJm9tSjFlCrbFNJ6AfEEHUJq5BW5CjEtSZD7FzSaiO+W+pXpMsYLcTRs0zGnyhB63AoQ0HLw== X-Received: by 2002:a17:903:2345:b0:1fd:6d4c:24e9 with SMTP id d9443c01a7336-1ff5722df70mr3471695ad.10.1722521179531; Thu, 01 Aug 2024 07:06:19 -0700 (PDT) From: Jim Shu To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Jim Shu Subject: [PATCH v2 2/3] hw/dma: xilinx_axidma: Send DMA error IRQ if any memory access is failed Date: Thu, 1 Aug 2024 22:06:08 +0800 Message-Id: <20240801140609.26922-3-jim.shu@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240801140609.26922-1-jim.shu@sifive.com> References: <20240801140609.26922-1-jim.shu@sifive.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=jim.shu@sifive.com; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1722521291640116600 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The memory transactions from DMA could have bus-error in some cases. If it is failed, DMA device should send error IRQs. Signed-off-by: Jim Shu --- hw/dma/trace-events | 1 + hw/dma/xilinx_axidma.c | 69 ++++++++++++++++++++++++++++++------------ 2 files changed, 50 insertions(+), 20 deletions(-) diff --git a/hw/dma/trace-events b/hw/dma/trace-events index 4c09790f9a..7db38e0e93 100644 --- a/hw/dma/trace-events +++ b/hw/dma/trace-events @@ -47,3 +47,4 @@ pl330_iomem_read(uint32_t addr, uint32_t data) "addr: 0x%= 08"PRIx32" data: 0x%08" =20 # xilinx_axidma.c xilinx_axidma_loading_desc_fail(uint32_t res) "error:%u" +xilinx_axidma_storing_desc_fail(uint32_t res) "error:%u" diff --git a/hw/dma/xilinx_axidma.c b/hw/dma/xilinx_axidma.c index 6aa8c9272c..728246f925 100644 --- a/hw/dma/xilinx_axidma.c +++ b/hw/dma/xilinx_axidma.c @@ -194,6 +194,20 @@ static inline int streamid_from_addr(hwaddr addr) return sid; } =20 +/* When DMA is error, fill in the register of this Stream. */ +static void stream_dma_error(struct Stream *s, MemTxResult result) +{ + if (result =3D=3D MEMTX_DECODE_ERROR) { + s->regs[R_DMASR] |=3D DMASR_DECERR; + } else { + s->regs[R_DMASR] |=3D DMASR_SLVERR; + } + + s->regs[R_DMACR] &=3D ~DMACR_RUNSTOP; + s->regs[R_DMASR] |=3D DMASR_HALTED; + s->regs[R_DMASR] |=3D DMASR_ERR_IRQ; +} + static MemTxResult stream_desc_load(struct Stream *s, hwaddr addr) { struct SDesc *d =3D &s->desc; @@ -203,16 +217,7 @@ static MemTxResult stream_desc_load(struct Stream *s, = hwaddr addr) d, sizeof *d); if (result !=3D MEMTX_OK) { trace_xilinx_axidma_loading_desc_fail(result); - - if (result =3D=3D MEMTX_DECODE_ERROR) { - s->regs[R_DMASR] |=3D DMASR_DECERR; - } else { - s->regs[R_DMASR] |=3D DMASR_SLVERR; - } - - s->regs[R_DMACR] &=3D ~DMACR_RUNSTOP; - s->regs[R_DMASR] |=3D DMASR_HALTED; - s->regs[R_DMASR] |=3D DMASR_ERR_IRQ; + stream_dma_error(s, result); return result; } =20 @@ -224,17 +229,24 @@ static MemTxResult stream_desc_load(struct Stream *s,= hwaddr addr) return result; } =20 -static void stream_desc_store(struct Stream *s, hwaddr addr) +static MemTxResult stream_desc_store(struct Stream *s, hwaddr addr) { struct SDesc *d =3D &s->desc; + MemTxResult result; =20 /* Convert from host endianness into LE. */ d->buffer_address =3D cpu_to_le64(d->buffer_address); d->nxtdesc =3D cpu_to_le64(d->nxtdesc); d->control =3D cpu_to_le32(d->control); d->status =3D cpu_to_le32(d->status); - address_space_write(&s->dma->as, addr, MEMTXATTRS_UNSPECIFIED, - d, sizeof *d); + result =3D address_space_write(&s->dma->as, addr, MEMTXATTRS_UNSPECIFI= ED, + d, sizeof *d); + + if (result !=3D MEMTX_OK) { + trace_xilinx_axidma_storing_desc_fail(result); + stream_dma_error(s, result); + } + return result; } =20 static void stream_update_irq(struct Stream *s) @@ -294,6 +306,7 @@ static void stream_process_mem2s(struct Stream *s, Stre= amSink *tx_data_dev, uint32_t txlen, origin_txlen; uint64_t addr; bool eop; + MemTxResult result; =20 if (!stream_running(s) || stream_idle(s) || stream_halted(s)) { return; @@ -322,9 +335,14 @@ static void stream_process_mem2s(struct Stream *s, Str= eamSink *tx_data_dev, unsigned int len; =20 len =3D txlen > sizeof s->txbuf ? sizeof s->txbuf : txlen; - address_space_read(&s->dma->as, addr, - MEMTXATTRS_UNSPECIFIED, - s->txbuf, len); + result =3D address_space_read(&s->dma->as, addr, + MEMTXATTRS_UNSPECIFIED, + s->txbuf, len); + if (result !=3D MEMTX_OK) { + stream_dma_error(s, result); + return; + } + stream_push(tx_data_dev, s->txbuf, len, eop && len =3D=3D txle= n); txlen -=3D len; addr +=3D len; @@ -336,7 +354,9 @@ static void stream_process_mem2s(struct Stream *s, Stre= amSink *tx_data_dev, =20 /* Update the descriptor. */ s->desc.status =3D origin_txlen | SDESC_STATUS_COMPLETE; - stream_desc_store(s, s->regs[R_CURDESC]); + if (stream_desc_store(s, s->regs[R_CURDESC]) !=3D MEMTX_OK) { + break; + } =20 /* Advance. */ prev_d =3D s->regs[R_CURDESC]; @@ -354,6 +374,7 @@ static size_t stream_process_s2mem(struct Stream *s, un= signed char *buf, uint32_t prev_d; unsigned int rxlen; size_t pos =3D 0; + MemTxResult result; =20 if (!stream_running(s) || stream_idle(s) || stream_halted(s)) { return 0; @@ -375,8 +396,13 @@ static size_t stream_process_s2mem(struct Stream *s, u= nsigned char *buf, rxlen =3D len; } =20 - address_space_write(&s->dma->as, s->desc.buffer_address, - MEMTXATTRS_UNSPECIFIED, buf + pos, rxlen); + result =3D address_space_write(&s->dma->as, s->desc.buffer_address, + MEMTXATTRS_UNSPECIFIED, buf + pos, rx= len); + if (result !=3D MEMTX_OK) { + stream_dma_error(s, result); + break; + } + len -=3D rxlen; pos +=3D rxlen; =20 @@ -389,7 +415,10 @@ static size_t stream_process_s2mem(struct Stream *s, u= nsigned char *buf, =20 s->desc.status |=3D s->sof << SDESC_STATUS_SOF_BIT; s->desc.status |=3D SDESC_STATUS_COMPLETE; - stream_desc_store(s, s->regs[R_CURDESC]); + result =3D stream_desc_store(s, s->regs[R_CURDESC]); + if (result !=3D MEMTX_OK) { + break; + } s->sof =3D eop; =20 /* Advance. */ --=20 2.17.1