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v2 4/4] hw/sd/sdhci: Check ADMA descriptors can be accessed Date: Wed, 31 Jul 2024 23:25:01 +0200 Message-ID: <20240731212501.44385-5-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240731212501.44385-1-philmd@linaro.org> References: <20240731212501.44385-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=philmd@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1722461160089116600 Since malicious guest can write invalid addresses to the ADMASYSADDR register, we need to check whether the descriptor could be correctly filled or not. Cc: qemu-stable@nongnu.org Fixes: d7dfca0807 ("hw/sdhci: introduce standard SD host controller") Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/sd/sdhci.c | 23 +++++++++++++++++------ 1 file changed, 17 insertions(+), 6 deletions(-) diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c index 2d8fa3151a..6794ee2267 100644 --- a/hw/sd/sdhci.c +++ b/hw/sd/sdhci.c @@ -701,13 +701,18 @@ static void trace_adma_description(const char *type, = const ADMADescr *dscr) static void get_adma_description(SDHCIState *s, ADMADescr *dscr) { hwaddr entry_addr =3D (hwaddr)s->admasysaddr; + MemTxResult res; + switch (SDHC_DMA_TYPE(s->hostctl1)) { case SDHC_CTRL_ADMA2_32: { uint64_t adma2 =3D 0; =20 - dma_memory_read(s->dma_as, entry_addr, &adma2, sizeof(adma2), - MEMTXATTRS_UNSPECIFIED); + res =3D dma_memory_read(s->dma_as, entry_addr, &adma2, sizeof(= adma2), + MEMTXATTRS_UNSPECIFIED); + if (res !=3D MEMTX_OK) { + break; + } adma2 =3D le64_to_cpu(adma2); /* * The spec does not specify endianness of descriptor table. @@ -724,8 +729,11 @@ static void get_adma_description(SDHCIState *s, ADMADe= scr *dscr) { uint32_t adma1 =3D 0; =20 - dma_memory_read(s->dma_as, entry_addr, &adma1, sizeof(adma1), - MEMTXATTRS_UNSPECIFIED); + res =3D dma_memory_read(s->dma_as, entry_addr, &adma1, sizeof(= adma1), + MEMTXATTRS_UNSPECIFIED); + if (res !=3D MEMTX_OK) { + break; + } adma1 =3D le32_to_cpu(adma1); dscr->addr =3D (hwaddr)(adma1 & ~0xfff); dscr->attr =3D (uint8_t)extract32(adma1, 0, 7); @@ -748,8 +756,11 @@ static void get_adma_description(SDHCIState *s, ADMADe= scr *dscr) } QEMU_PACKED adma2; QEMU_BUILD_BUG_ON(sizeof(adma2) !=3D 12); =20 - dma_memory_read(s->dma_as, entry_addr, &adma2, sizeof(adma2), - MEMTXATTRS_UNSPECIFIED); + res =3D dma_memory_read(s->dma_as, entry_addr, &adma2, sizeof(= adma2), + MEMTXATTRS_UNSPECIFIED); + if (res !=3D MEMTX_OK) { + break; + } dscr->length =3D le16_to_cpu(adma2.length); dscr->addr =3D le64_to_cpu(adma2.addr); dscr->attr =3D adma2.attr & (uint8_t) ~0xc0; --=20 2.45.2