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b=Zmob4F3Mzgkgc0WqicClJphaLPOhU wxe1yi5rJr6yXp+zlfY1J6vZ7tDCLVVkdTuEZ/c2Rub9Z2f6p993s0rpLlROwBKk neGdTfDUtUrW4OnnntbkvCFgohj/jtzEP+F7VF864xz5TZBYIZdJj6riCYgrdVm4 ncyXCCUmUQldWC+9ru9W8loyOGk6d+2LtbntLo8vMOjd++GFMN/ImgdCmmy+akuy RVq5ooNV+x8EPD9pQrP4GiIjQaCySkVwKCySEBgs1CRTyyTZ5RsMph1fAF4j6I1U i5e8bBKn3SLr3ERsY6Y11vok/a6mzFN0VjwcJH7wfPQgrL/HDCVXTTduA== From: Aditya Gupta To: Mahesh J Salgaonkar , Madhavan Srinivasan , Nicholas Piggin , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Harsh Prateek Bora Cc: , Subject: [PATCH v6 RESEND 1/5] target/ppc: Reduce code duplication across Power9/10 init code Date: Wed, 31 Jul 2024 11:20:18 +0530 Message-ID: <20240731055022.696051-2-adityag@linux.ibm.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240731055022.696051-1-adityag@linux.ibm.com> References: <20240731055022.696051-1-adityag@linux.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-GUID: wYQ2JBTCFErospt2cyoGwCPs_YVgf1-i X-Proofpoint-ORIG-GUID: J-_55_vm21YB4Spy4ydEnrKhCugdY5xo X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-07-31_02,2024-07-30_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 lowpriorityscore=0 spamscore=0 impostorscore=0 adultscore=0 clxscore=1015 priorityscore=1501 bulkscore=0 malwarescore=0 mlxlogscore=999 phishscore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2407310039 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=148.163.158.5; envelope-from=adityag@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H3=-0.01, RCVD_IN_MSPIKE_WL=-0.01, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, UPPERCASE_50_75=0.008 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1722405100808116600 Content-Type: text/plain; charset="utf-8" From: Harsh Prateek Bora Power9/10 initialization code consists of a lot of logical OR of various flag bits as supported by respective Power platform during its initialization, most of which is duplicated and only selected bits are added or removed as needed with each new platform support being added. Remove the duplicate code and share using common macros. Reviewed-by: Nicholas Piggin Signed-off-by: Harsh Prateek Bora [adityag: renamed many POWERPC_* flags to PPC_* flags, checkpatch fixes] Signed-off-by: Aditya Gupta --- target/ppc/cpu_init.c | 124 +++++------------------------------------- target/ppc/cpu_init.h | 84 ++++++++++++++++++++++++++++ 2 files changed, 99 insertions(+), 109 deletions(-) create mode 100644 target/ppc/cpu_init.h diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 23881d09e9f3..4c7368cfaeb5 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -52,6 +52,7 @@ #include "kvm_ppc.h" #endif =20 +#include "cpu_init.h" /* #define PPC_DEBUG_SPR */ /* #define USE_APPLE_GDB */ =20 @@ -6510,58 +6511,15 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data) dc->fw_name =3D "PowerPC,POWER9"; dc->desc =3D "POWER9"; pcc->pvr_match =3D ppc_pvr_match_power9; - pcc->pcr_mask =3D PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07; - pcc->pcr_supported =3D PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | PCR_COMPAT_= 2_06 | - PCR_COMPAT_2_05; + pcc->pcr_mask =3D PPC_PCR_MASK_POWER9; + pcc->pcr_supported =3D PPC_PCR_SUPPORTED_POWER9; pcc->init_proc =3D init_proc_POWER9; pcc->check_pow =3D check_pow_nocheck; pcc->check_attn =3D check_attn_hid0_power9; - pcc->insns_flags =3D PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB= | - PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | - PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | - PPC_FLOAT_FRSQRTES | - PPC_FLOAT_STFIWX | - PPC_FLOAT_EXT | - PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | - PPC_MEM_SYNC | PPC_MEM_EIEIO | - PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | - PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | - PPC_SEGMENT_64B | PPC_SLBI | - PPC_POPCNTB | PPC_POPCNTWD | - PPC_CILDST; - pcc->insns_flags2 =3D PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | - PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | - PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | - PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | - PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | - PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | - PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL | PPC2_MEM_LWS= YNC | - PPC2_BCDA_ISA206; - pcc->msr_mask =3D (1ull << MSR_SF) | - (1ull << MSR_HV) | - (1ull << MSR_TM) | - (1ull << MSR_VR) | - (1ull << MSR_VSX) | - (1ull << MSR_EE) | - (1ull << MSR_PR) | - (1ull << MSR_FP) | - (1ull << MSR_ME) | - (1ull << MSR_FE0) | - (1ull << MSR_SE) | - (1ull << MSR_DE) | - (1ull << MSR_FE1) | - (1ull << MSR_IR) | - (1ull << MSR_DR) | - (1ull << MSR_PMM) | - (1ull << MSR_RI) | - (1ull << MSR_LE); - pcc->lpcr_mask =3D LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD | - (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL | - LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD | - (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE | - LPCR_DEE | LPCR_OEE)) - | LPCR_MER | LPCR_GTSE | LPCR_TC | - LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE; + pcc->insns_flags =3D PPC_INSNS_FLAGS_POWER9; + pcc->insns_flags2 =3D PPC_INSNS_FLAGS2_POWER9; + pcc->msr_mask =3D PPC_MSR_MASK_POWER9; + pcc->lpcr_mask =3D PPC_LPCR_MASK_POWER9; pcc->lpcr_pm =3D LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OE= E; pcc->mmu_model =3D POWERPC_MMU_3_00; #if !defined(CONFIG_USER_ONLY) @@ -6574,10 +6532,7 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data) pcc->excp_model =3D POWERPC_EXCP_POWER9; pcc->bus_model =3D PPC_FLAGS_INPUT_POWER9; pcc->bfd_mach =3D bfd_mach_ppc64; - pcc->flags =3D POWERPC_FLAG_VRE | POWERPC_FLAG_SE | - POWERPC_FLAG_BE | POWERPC_FLAG_PMM | - POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | - POWERPC_FLAG_VSX | POWERPC_FLAG_TM | POWERPC_FLAG_SCV; + pcc->flags =3D POWERPC_FLAGS_POWER9; pcc->l1_dcache_size =3D 0x8000; pcc->l1_icache_size =3D 0x8000; } @@ -6690,60 +6645,15 @@ POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data) dc->fw_name =3D "PowerPC,POWER10"; dc->desc =3D "POWER10"; pcc->pvr_match =3D ppc_pvr_match_power10; - pcc->pcr_mask =3D PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07 | - PCR_COMPAT_3_00; - pcc->pcr_supported =3D PCR_COMPAT_3_10 | PCR_COMPAT_3_00 | PCR_COMPAT_= 2_07 | - PCR_COMPAT_2_06 | PCR_COMPAT_2_05; + pcc->pcr_mask =3D PPC_PCR_MASK_POWER10; + pcc->pcr_supported =3D PPC_PCR_SUPPORTED_POWER10; pcc->init_proc =3D init_proc_POWER10; pcc->check_pow =3D check_pow_nocheck; pcc->check_attn =3D check_attn_hid0_power9; - pcc->insns_flags =3D PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB= | - PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | - PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | - PPC_FLOAT_FRSQRTES | - PPC_FLOAT_STFIWX | - PPC_FLOAT_EXT | - PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | - PPC_MEM_SYNC | PPC_MEM_EIEIO | - PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | - PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | - PPC_SEGMENT_64B | PPC_SLBI | - PPC_POPCNTB | PPC_POPCNTWD | - PPC_CILDST; - pcc->insns_flags2 =3D PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | - PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | - PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | - PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | - PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | - PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | - PPC2_ISA300 | PPC2_PRCNTL | PPC2_ISA310 | - PPC2_MEM_LWSYNC | PPC2_BCDA_ISA206; - pcc->msr_mask =3D (1ull << MSR_SF) | - (1ull << MSR_HV) | - (1ull << MSR_VR) | - (1ull << MSR_VSX) | - (1ull << MSR_EE) | - (1ull << MSR_PR) | - (1ull << MSR_FP) | - (1ull << MSR_ME) | - (1ull << MSR_FE0) | - (1ull << MSR_SE) | - (1ull << MSR_DE) | - (1ull << MSR_FE1) | - (1ull << MSR_IR) | - (1ull << MSR_DR) | - (1ull << MSR_PMM) | - (1ull << MSR_RI) | - (1ull << MSR_LE); - pcc->lpcr_mask =3D LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD | - (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL | - LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD | - (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE | - LPCR_DEE | LPCR_OEE)) - | LPCR_MER | LPCR_GTSE | LPCR_TC | - LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE; - /* DD2 adds an extra HAIL bit */ - pcc->lpcr_mask |=3D LPCR_HAIL; + pcc->insns_flags =3D PPC_INSNS_FLAGS_POWER10; + pcc->insns_flags2 =3D PPC_INSNS_FLAGS2_POWER10; + pcc->msr_mask =3D PPC_MSR_MASK_POWER10; + pcc->lpcr_mask =3D PPC_LPCR_MASK_POWER10; =20 pcc->lpcr_pm =3D LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OE= E; pcc->mmu_model =3D POWERPC_MMU_3_00; @@ -6756,11 +6666,7 @@ POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data) pcc->excp_model =3D POWERPC_EXCP_POWER10; pcc->bus_model =3D PPC_FLAGS_INPUT_POWER9; pcc->bfd_mach =3D bfd_mach_ppc64; - pcc->flags =3D POWERPC_FLAG_VRE | POWERPC_FLAG_SE | - POWERPC_FLAG_BE | POWERPC_FLAG_PMM | - POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | - POWERPC_FLAG_VSX | POWERPC_FLAG_SCV | - POWERPC_FLAG_BHRB; + pcc->flags =3D POWERPC_FLAGS_POWER10; pcc->l1_dcache_size =3D 0x8000; pcc->l1_icache_size =3D 0x8000; } diff --git a/target/ppc/cpu_init.h b/target/ppc/cpu_init.h new file mode 100644 index 000000000000..7479b59da73b --- /dev/null +++ b/target/ppc/cpu_init.h @@ -0,0 +1,84 @@ +#ifndef TARGET_PPC_CPU_INIT_H +#define TARGET_PPC_CPU_INIT_H + +#define PPC_INSNS_FLAGS_POWER9 \ + PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | \ + PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \ + PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | PPC_FLOAT_FRSQRTES | \ + PPC_FLOAT_STFIWX | PPC_FLOAT_EXT | PPC_CACHE | PPC_CACHE_ICBI | \ + PPC_CACHE_DCBZ | PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | \ + PPC_MEM_TLBSYNC | PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | \ + PPC_SEGMENT_64B | PPC_SLBI | PPC_POPCNTB | PPC_POPCNTWD | \ + PPC_CILDST + +#define PPC_INSNS_FLAGS_POWER10 PPC_INSNS_FLAGS_POWER9 + +#define PPC_INSNS_FLAGS2_POWER_COMMON \ + PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | \ + PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | \ + PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | \ + PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | PPC2_ISA205 | \ + PPC2_ISA207S | PPC2_FP_CVT_S64 | PPC2_ISA300 | PPC2_PRCNTL | \ + PPC2_MEM_LWSYNC | PPC2_BCDA_ISA206 + +#define PPC_INSNS_FLAGS2_POWER9 \ + PPC_INSNS_FLAGS2_POWER_COMMON | PPC2_TM +#define PPC_INSNS_FLAGS2_POWER10 \ + PPC_INSNS_FLAGS2_POWER_COMMON | PPC2_ISA310 + +#define PPC_MSR_MASK_POWER_COMMON \ + (1ull << MSR_SF) | \ + (1ull << MSR_HV) | \ + (1ull << MSR_VR) | \ + (1ull << MSR_VSX) | \ + (1ull << MSR_EE) | \ + (1ull << MSR_PR) | \ + (1ull << MSR_FP) | \ + (1ull << MSR_ME) | \ + (1ull << MSR_FE0) | \ + (1ull << MSR_SE) | \ + (1ull << MSR_DE) | \ + (1ull << MSR_FE1) | \ + (1ull << MSR_IR) | \ + (1ull << MSR_DR) | \ + (1ull << MSR_PMM) | \ + (1ull << MSR_RI) | \ + (1ull << MSR_LE) + +#define PPC_MSR_MASK_POWER9 \ + PPC_MSR_MASK_POWER_COMMON | (1ull << MSR_TM) +#define PPC_MSR_MASK_POWER10 \ + PPC_MSR_MASK_POWER_COMMON + +#define PPC_PCR_MASK_POWER9 \ + PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07 +#define PPC_PCR_MASK_POWER10 \ + PPC_PCR_MASK_POWER9 | PCR_COMPAT_3_00 + +#define PPC_PCR_SUPPORTED_POWER9 \ + PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05 +#define PPC_PCR_SUPPORTED_POWER10 \ + PPC_PCR_SUPPORTED_POWER9 | PCR_COMPAT_3_10 + +#define PPC_LPCR_MASK_POWER9 = \ + LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD | = \ + (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL | = \ + LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD | = \ + (LPCR_PECE_L_MASK & (LPCR_PDEE|LPCR_HDEE|LPCR_EEE|LPCR_DEE|LPCR_OEE)) = | \ + LPCR_MER | LPCR_GTSE | LPCR_TC | LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE |= \ + LPCR_HDICE +/* DD2 adds an extra HAIL bit */ +#define PPC_LPCR_MASK_POWER10 \ + PPC_LPCR_MASK_POWER9 | LPCR_HAIL + +#define POWERPC_FLAGS_POWER_COMMON \ + POWERPC_FLAG_VRE | POWERPC_FLAG_SE | POWERPC_FLAG_BE | \ + POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | \ + POWERPC_FLAG_VSX | POWERPC_FLAG_SCV + +#define POWERPC_FLAGS_POWER9 \ + POWERPC_FLAGS_POWER_COMMON | POWERPC_FLAG_TM +#define POWERPC_FLAGS_POWER10 \ + POWERPC_FLAGS_POWER_COMMON | POWERPC_FLAG_BHRB + +#endif /* TARGET_PPC_CPU_INIT_H */ --=20 2.45.2