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b=Zmob4F3Mzgkgc0WqicClJphaLPOhU wxe1yi5rJr6yXp+zlfY1J6vZ7tDCLVVkdTuEZ/c2Rub9Z2f6p993s0rpLlROwBKk neGdTfDUtUrW4OnnntbkvCFgohj/jtzEP+F7VF864xz5TZBYIZdJj6riCYgrdVm4 ncyXCCUmUQldWC+9ru9W8loyOGk6d+2LtbntLo8vMOjd++GFMN/ImgdCmmy+akuy RVq5ooNV+x8EPD9pQrP4GiIjQaCySkVwKCySEBgs1CRTyyTZ5RsMph1fAF4j6I1U i5e8bBKn3SLr3ERsY6Y11vok/a6mzFN0VjwcJH7wfPQgrL/HDCVXTTduA== From: Aditya Gupta To: Mahesh J Salgaonkar , Madhavan Srinivasan , Nicholas Piggin , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Harsh Prateek Bora Cc: , Subject: [PATCH v6 RESEND 1/5] target/ppc: Reduce code duplication across Power9/10 init code Date: Wed, 31 Jul 2024 11:20:18 +0530 Message-ID: <20240731055022.696051-2-adityag@linux.ibm.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240731055022.696051-1-adityag@linux.ibm.com> References: <20240731055022.696051-1-adityag@linux.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-GUID: wYQ2JBTCFErospt2cyoGwCPs_YVgf1-i X-Proofpoint-ORIG-GUID: J-_55_vm21YB4Spy4ydEnrKhCugdY5xo X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-07-31_02,2024-07-30_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 lowpriorityscore=0 spamscore=0 impostorscore=0 adultscore=0 clxscore=1015 priorityscore=1501 bulkscore=0 malwarescore=0 mlxlogscore=999 phishscore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2407310039 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=148.163.158.5; envelope-from=adityag@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H3=-0.01, RCVD_IN_MSPIKE_WL=-0.01, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, UPPERCASE_50_75=0.008 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1722405100808116600 Content-Type: text/plain; charset="utf-8" From: Harsh Prateek Bora Power9/10 initialization code consists of a lot of logical OR of various flag bits as supported by respective Power platform during its initialization, most of which is duplicated and only selected bits are added or removed as needed with each new platform support being added. Remove the duplicate code and share using common macros. Reviewed-by: Nicholas Piggin Signed-off-by: Harsh Prateek Bora [adityag: renamed many POWERPC_* flags to PPC_* flags, checkpatch fixes] Signed-off-by: Aditya Gupta Tested-by: Amit Machhiwal --- target/ppc/cpu_init.c | 124 +++++------------------------------------- target/ppc/cpu_init.h | 84 ++++++++++++++++++++++++++++ 2 files changed, 99 insertions(+), 109 deletions(-) create mode 100644 target/ppc/cpu_init.h diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 23881d09e9f3..4c7368cfaeb5 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -52,6 +52,7 @@ #include "kvm_ppc.h" #endif =20 +#include "cpu_init.h" /* #define PPC_DEBUG_SPR */ /* #define USE_APPLE_GDB */ =20 @@ -6510,58 +6511,15 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data) dc->fw_name =3D "PowerPC,POWER9"; dc->desc =3D "POWER9"; pcc->pvr_match =3D ppc_pvr_match_power9; - pcc->pcr_mask =3D PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07; - pcc->pcr_supported =3D PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | PCR_COMPAT_= 2_06 | - PCR_COMPAT_2_05; + pcc->pcr_mask =3D PPC_PCR_MASK_POWER9; + pcc->pcr_supported =3D PPC_PCR_SUPPORTED_POWER9; pcc->init_proc =3D init_proc_POWER9; pcc->check_pow =3D check_pow_nocheck; pcc->check_attn =3D check_attn_hid0_power9; - pcc->insns_flags =3D PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB= | - PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | - PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | - PPC_FLOAT_FRSQRTES | - PPC_FLOAT_STFIWX | - PPC_FLOAT_EXT | - PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | - PPC_MEM_SYNC | PPC_MEM_EIEIO | - PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | - PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | - PPC_SEGMENT_64B | PPC_SLBI | - PPC_POPCNTB | PPC_POPCNTWD | - PPC_CILDST; - pcc->insns_flags2 =3D PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | - PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | - PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | - PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | - PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | - PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | - PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL | PPC2_MEM_LWS= YNC | - PPC2_BCDA_ISA206; - pcc->msr_mask =3D (1ull << MSR_SF) | - (1ull << MSR_HV) | - (1ull << MSR_TM) | - (1ull << MSR_VR) | - (1ull << MSR_VSX) | - (1ull << MSR_EE) | - (1ull << MSR_PR) | - (1ull << MSR_FP) | - (1ull << MSR_ME) | - (1ull << MSR_FE0) | - (1ull << MSR_SE) | - (1ull << MSR_DE) | - (1ull << MSR_FE1) | - (1ull << MSR_IR) | - (1ull << MSR_DR) | - (1ull << MSR_PMM) | - (1ull << MSR_RI) | - (1ull << MSR_LE); - pcc->lpcr_mask =3D LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD | - (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL | - LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD | - (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE | - LPCR_DEE | LPCR_OEE)) - | LPCR_MER | LPCR_GTSE | LPCR_TC | - LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE; + pcc->insns_flags =3D PPC_INSNS_FLAGS_POWER9; + pcc->insns_flags2 =3D PPC_INSNS_FLAGS2_POWER9; + pcc->msr_mask =3D PPC_MSR_MASK_POWER9; + pcc->lpcr_mask =3D PPC_LPCR_MASK_POWER9; pcc->lpcr_pm =3D LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OE= E; pcc->mmu_model =3D POWERPC_MMU_3_00; #if !defined(CONFIG_USER_ONLY) @@ -6574,10 +6532,7 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data) pcc->excp_model =3D POWERPC_EXCP_POWER9; pcc->bus_model =3D PPC_FLAGS_INPUT_POWER9; pcc->bfd_mach =3D bfd_mach_ppc64; - pcc->flags =3D POWERPC_FLAG_VRE | POWERPC_FLAG_SE | - POWERPC_FLAG_BE | POWERPC_FLAG_PMM | - POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | - POWERPC_FLAG_VSX | POWERPC_FLAG_TM | POWERPC_FLAG_SCV; + pcc->flags =3D POWERPC_FLAGS_POWER9; pcc->l1_dcache_size =3D 0x8000; pcc->l1_icache_size =3D 0x8000; } @@ -6690,60 +6645,15 @@ POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data) dc->fw_name =3D "PowerPC,POWER10"; dc->desc =3D "POWER10"; pcc->pvr_match =3D ppc_pvr_match_power10; - pcc->pcr_mask =3D PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07 | - PCR_COMPAT_3_00; - pcc->pcr_supported =3D PCR_COMPAT_3_10 | PCR_COMPAT_3_00 | PCR_COMPAT_= 2_07 | - PCR_COMPAT_2_06 | PCR_COMPAT_2_05; + pcc->pcr_mask =3D PPC_PCR_MASK_POWER10; + pcc->pcr_supported =3D PPC_PCR_SUPPORTED_POWER10; pcc->init_proc =3D init_proc_POWER10; pcc->check_pow =3D check_pow_nocheck; pcc->check_attn =3D check_attn_hid0_power9; - pcc->insns_flags =3D PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB= | - PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | - PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | - PPC_FLOAT_FRSQRTES | - PPC_FLOAT_STFIWX | - PPC_FLOAT_EXT | - PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | - PPC_MEM_SYNC | PPC_MEM_EIEIO | - PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | - PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | - PPC_SEGMENT_64B | PPC_SLBI | - PPC_POPCNTB | PPC_POPCNTWD | - PPC_CILDST; - pcc->insns_flags2 =3D PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | - PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | - PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | - PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | - PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | - PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | - PPC2_ISA300 | PPC2_PRCNTL | PPC2_ISA310 | - PPC2_MEM_LWSYNC | PPC2_BCDA_ISA206; - pcc->msr_mask =3D (1ull << MSR_SF) | - (1ull << MSR_HV) | - (1ull << MSR_VR) | - (1ull << MSR_VSX) | - (1ull << MSR_EE) | - (1ull << MSR_PR) | - (1ull << MSR_FP) | - (1ull << MSR_ME) | - (1ull << MSR_FE0) | - (1ull << MSR_SE) | - (1ull << MSR_DE) | - (1ull << MSR_FE1) | - (1ull << MSR_IR) | - (1ull << MSR_DR) | - (1ull << MSR_PMM) | - (1ull << MSR_RI) | - (1ull << MSR_LE); - pcc->lpcr_mask =3D LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD | - (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL | - LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD | - (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE | - LPCR_DEE | LPCR_OEE)) - | LPCR_MER | LPCR_GTSE | LPCR_TC | - LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE; - /* DD2 adds an extra HAIL bit */ - pcc->lpcr_mask |=3D LPCR_HAIL; + pcc->insns_flags =3D PPC_INSNS_FLAGS_POWER10; + pcc->insns_flags2 =3D PPC_INSNS_FLAGS2_POWER10; + pcc->msr_mask =3D PPC_MSR_MASK_POWER10; + pcc->lpcr_mask =3D PPC_LPCR_MASK_POWER10; =20 pcc->lpcr_pm =3D LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OE= E; pcc->mmu_model =3D POWERPC_MMU_3_00; @@ -6756,11 +6666,7 @@ POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data) pcc->excp_model =3D POWERPC_EXCP_POWER10; pcc->bus_model =3D PPC_FLAGS_INPUT_POWER9; pcc->bfd_mach =3D bfd_mach_ppc64; - pcc->flags =3D POWERPC_FLAG_VRE | POWERPC_FLAG_SE | - POWERPC_FLAG_BE | POWERPC_FLAG_PMM | - POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | - POWERPC_FLAG_VSX | POWERPC_FLAG_SCV | - POWERPC_FLAG_BHRB; + pcc->flags =3D POWERPC_FLAGS_POWER10; pcc->l1_dcache_size =3D 0x8000; pcc->l1_icache_size =3D 0x8000; } diff --git a/target/ppc/cpu_init.h b/target/ppc/cpu_init.h new file mode 100644 index 000000000000..7479b59da73b --- /dev/null +++ b/target/ppc/cpu_init.h @@ -0,0 +1,84 @@ +#ifndef TARGET_PPC_CPU_INIT_H +#define TARGET_PPC_CPU_INIT_H + +#define PPC_INSNS_FLAGS_POWER9 \ + PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | \ + PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \ + PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | PPC_FLOAT_FRSQRTES | \ + PPC_FLOAT_STFIWX | PPC_FLOAT_EXT | PPC_CACHE | PPC_CACHE_ICBI | \ + PPC_CACHE_DCBZ | PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | \ + PPC_MEM_TLBSYNC | PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | \ + PPC_SEGMENT_64B | PPC_SLBI | PPC_POPCNTB | PPC_POPCNTWD | \ + PPC_CILDST + +#define PPC_INSNS_FLAGS_POWER10 PPC_INSNS_FLAGS_POWER9 + +#define PPC_INSNS_FLAGS2_POWER_COMMON \ + PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | \ + PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | \ + PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | \ + PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | PPC2_ISA205 | \ + PPC2_ISA207S | PPC2_FP_CVT_S64 | PPC2_ISA300 | PPC2_PRCNTL | \ + PPC2_MEM_LWSYNC | PPC2_BCDA_ISA206 + +#define PPC_INSNS_FLAGS2_POWER9 \ + PPC_INSNS_FLAGS2_POWER_COMMON | PPC2_TM +#define PPC_INSNS_FLAGS2_POWER10 \ + PPC_INSNS_FLAGS2_POWER_COMMON | PPC2_ISA310 + +#define PPC_MSR_MASK_POWER_COMMON \ + (1ull << MSR_SF) | \ + (1ull << MSR_HV) | \ + (1ull << MSR_VR) | \ + (1ull << MSR_VSX) | \ + (1ull << MSR_EE) | \ + (1ull << MSR_PR) | \ + (1ull << MSR_FP) | \ + (1ull << MSR_ME) | \ + (1ull << MSR_FE0) | \ + (1ull << MSR_SE) | \ + (1ull << MSR_DE) | \ + (1ull << MSR_FE1) | \ + (1ull << MSR_IR) | \ + (1ull << MSR_DR) | \ + (1ull << MSR_PMM) | \ + (1ull << MSR_RI) | \ + (1ull << MSR_LE) + +#define PPC_MSR_MASK_POWER9 \ + PPC_MSR_MASK_POWER_COMMON | (1ull << MSR_TM) +#define PPC_MSR_MASK_POWER10 \ + PPC_MSR_MASK_POWER_COMMON + +#define PPC_PCR_MASK_POWER9 \ + PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07 +#define PPC_PCR_MASK_POWER10 \ + PPC_PCR_MASK_POWER9 | PCR_COMPAT_3_00 + +#define PPC_PCR_SUPPORTED_POWER9 \ + PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05 +#define PPC_PCR_SUPPORTED_POWER10 \ + PPC_PCR_SUPPORTED_POWER9 | PCR_COMPAT_3_10 + +#define PPC_LPCR_MASK_POWER9 = \ + LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD | = \ + (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL | = \ + LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD | = \ + (LPCR_PECE_L_MASK & (LPCR_PDEE|LPCR_HDEE|LPCR_EEE|LPCR_DEE|LPCR_OEE)) = | \ + LPCR_MER | LPCR_GTSE | LPCR_TC | LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE |= \ + LPCR_HDICE +/* DD2 adds an extra HAIL bit */ +#define PPC_LPCR_MASK_POWER10 \ + PPC_LPCR_MASK_POWER9 | LPCR_HAIL + +#define POWERPC_FLAGS_POWER_COMMON \ + POWERPC_FLAG_VRE | POWERPC_FLAG_SE | POWERPC_FLAG_BE | \ + POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | \ + POWERPC_FLAG_VSX | POWERPC_FLAG_SCV + +#define POWERPC_FLAGS_POWER9 \ + POWERPC_FLAGS_POWER_COMMON | POWERPC_FLAG_TM +#define POWERPC_FLAGS_POWER10 \ + POWERPC_FLAGS_POWER_COMMON | POWERPC_FLAG_BHRB + +#endif /* TARGET_PPC_CPU_INIT_H */ --=20 2.45.2 From nobody Sun Nov 24 13:49:26 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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b=fpeVvfQ+TlteR8w6 8LI2MgH9yialpcWuEdngi4qoEp8blgWhqHBpmVFzbiVqxM2G2hZNA0680I+PtajJ zPyppoRcukRZCjCQncUv3277DeJ5PPsI8kQsyLCv48ZYqWng1yJINWzoJtfiKDQu hW1kxBsXHJqNYNItTGcayJAIgLFj59LmvIc9WDDbOe0BUAInwUrLtZb1vctkvIDq b5FRUtWTK7xO38vpxAf85pgDAkfz0ICeEjSofLQ2v7xa8L/LNpE0GdugTKUB8z8Q nD5+X3LOj2HuRUZe/XVZQdO1/UEJWb/HeyIFpGehZ6Da0n6EhbY4zo82/9SrqT+Q K6lXtg== From: Aditya Gupta To: Mahesh J Salgaonkar , Madhavan Srinivasan , Nicholas Piggin , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Harsh Prateek Bora Cc: , , Daniel Henrique Barboza Subject: [PATCH v6 RESEND 2/5] target/ppc: Introduce 'PowerPCCPUClass::spapr_logical_pvr' Date: Wed, 31 Jul 2024 11:20:19 +0530 Message-ID: <20240731055022.696051-3-adityag@linux.ibm.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240731055022.696051-1-adityag@linux.ibm.com> References: <20240731055022.696051-1-adityag@linux.ibm.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-GUID: pOT5LvlL9QDI8M1LQ60buGPrFrqNWj88 X-Proofpoint-ORIG-GUID: NXoJVBYR6iyw_r89y9nZq8Vviri2xT13 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-07-31_02,2024-07-30_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 mlxscore=0 lowpriorityscore=0 impostorscore=0 mlxlogscore=999 malwarescore=0 priorityscore=1501 bulkscore=0 adultscore=0 suspectscore=0 clxscore=1015 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2407310039 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=adityag@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H3=-0.01, RCVD_IN_MSPIKE_WL=-0.01, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1722405112224116600 Introduce 'PnvChipClass::spapr_logical_pvr' to know corresponding logical PVR of a PowerPC CPU. This helps to have a one-to-one mapping between PVR and logical PVR for a CPU, and used in a later commit to handle cases where PCR of two generations of Power chip is same, which causes regressions with compat-mode. Cc: C=C3=A9dric Le Goater Cc: Daniel Henrique Barboza Cc: Harsh Prateek Bora Cc: Mahesh J Salgaonkar Cc: Madhavan Srinivasan Cc: Nicholas Piggin Reviewed-by: Nicholas Piggin Signed-off-by: Aditya Gupta Tested-by: Amit Machhiwal --- target/ppc/cpu.h | 1 + target/ppc/cpu_init.c | 4 ++++ 2 files changed, 5 insertions(+) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 321ed2da75b7..752e11204b35 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1482,6 +1482,7 @@ struct PowerPCCPUClass { void (*parent_parse_features)(const char *type, char *str, Error **err= p); =20 uint32_t pvr; + uint32_t spapr_logical_pvr; /* * If @best is false, match if pcc is in the family of pvr * Else match only if pcc is the best match for pvr in this family. diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 4c7368cfaeb5..c5cd4133ea2f 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -6154,6 +6154,7 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data) =20 dc->fw_name =3D "PowerPC,POWER7"; dc->desc =3D "POWER7"; + pcc->spapr_logical_pvr =3D CPU_POWERPC_LOGICAL_2_06_PLUS; pcc->pvr_match =3D ppc_pvr_match_power7; pcc->pcr_mask =3D PCR_VEC_DIS | PCR_VSX_DIS | PCR_COMPAT_2_05; pcc->pcr_supported =3D PCR_COMPAT_2_06 | PCR_COMPAT_2_05; @@ -6317,6 +6318,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) =20 dc->fw_name =3D "PowerPC,POWER8"; dc->desc =3D "POWER8"; + pcc->spapr_logical_pvr =3D CPU_POWERPC_LOGICAL_2_07; pcc->pvr_match =3D ppc_pvr_match_power8; pcc->pcr_mask =3D PCR_TM_DIS | PCR_COMPAT_2_06 | PCR_COMPAT_2_05; pcc->pcr_supported =3D PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_COMPAT_= 2_05; @@ -6510,6 +6512,7 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data) =20 dc->fw_name =3D "PowerPC,POWER9"; dc->desc =3D "POWER9"; + pcc->spapr_logical_pvr =3D CPU_POWERPC_LOGICAL_3_00; pcc->pvr_match =3D ppc_pvr_match_power9; pcc->pcr_mask =3D PPC_PCR_MASK_POWER9; pcc->pcr_supported =3D PPC_PCR_SUPPORTED_POWER9; @@ -6644,6 +6647,7 @@ POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data) =20 dc->fw_name =3D "PowerPC,POWER10"; dc->desc =3D "POWER10"; + pcc->spapr_logical_pvr =3D CPU_POWERPC_LOGICAL_3_10; pcc->pvr_match =3D ppc_pvr_match_power10; pcc->pcr_mask =3D PPC_PCR_MASK_POWER10; pcc->pcr_supported =3D PPC_PCR_SUPPORTED_POWER10; --=20 2.45.2 From nobody Sun Nov 24 13:49:26 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=linux.ibm.com ARC-Seal: i=1; a=rsa-sha256; t=1722405098; cv=none; d=zohomail.com; s=zohoarc; b=bb3P0lWP9E6IEnXK/d1GGhMsnzDG2OMhcinztH4weBeKjmPFPeJaUsNgGp4am9/f7OimaULWZkHO3LCSjnZ6ABtaVMi1PVpC36YwpVvxuKtrBboHMWtr+otrFe/gkxC7TpdcUAjLf7aC20GUw8JmQExaL71ELv98Z7qfRuymIOQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1722405098; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Wed, 31 Jul 2024 05:50:29 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-type:content-transfer-encoding; s=pp1; bh= NdE/Fyel2C7AFtVEeKtdExqkuy8FZQ5dd9vlztjZABc=; b=gCQoZ2tSDDPBUCCT A+ejLfUQt5Vin6vkNAAo9Cm9K0iJsWWya9VkzhazvFv7rpJgMjpV45MpFhDpICVj lyoD3zxObKg/WuONihTALo6yOYgTK/KCPRkIvyzwuTjSbBr/hhgHVeib3oajkkp1 TO8K5gjbbN00mXPKWwbyf0wrlbcGhff/UAhT7Y+6gmWEbz0Kyapgq/tvyfm1hgpu tV1e64p4yptYI9fgeS+HYe+600QtfXz+WDYgQjlbyYL3ExzjUZgkBupcug1oD1LL Kgfbq87jrnncpGMoOxJOeR6Px5JUz2w9KV6hlUWX7jrSUKt2Rtw475ByMQ5whaGA l9aiTg== From: Aditya Gupta To: Mahesh J Salgaonkar , Madhavan Srinivasan , Nicholas Piggin , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Harsh Prateek Bora Cc: , , Daniel Henrique Barboza Subject: [PATCH v6 RESEND 3/5] target/ppc: Fix regression due to Power10 and Power11 having same PCR Date: Wed, 31 Jul 2024 11:20:20 +0530 Message-ID: <20240731055022.696051-4-adityag@linux.ibm.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240731055022.696051-1-adityag@linux.ibm.com> References: <20240731055022.696051-1-adityag@linux.ibm.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: 1undvf2mfXac0xn0IF91kFSN7ImfIiS- X-Proofpoint-GUID: p30L59jvZik3sFtGckDO9bm-pWPxCVbp X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-07-31_02,2024-07-30_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 suspectscore=0 mlxlogscore=909 clxscore=1015 phishscore=0 mlxscore=0 priorityscore=1501 bulkscore=0 adultscore=0 lowpriorityscore=0 spamscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2407310039 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=adityag@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H3=-0.01, RCVD_IN_MSPIKE_WL=-0.01, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1722405100776116600 Power11 has the same PCR (Processor Compatibility Register) value, as Power10. Due to this, QEMU considers Power11 as a valid compat-mode for Power10, ie. earlier it was possible to run QEMU with '-M pseries,max-compat-mode=3D= power11 --cpu power10' Same PCR also introduced a regression where `-M pseries --cpu power10` boots as Power11 (ie. logical PVR is of Power11, even though PVR is Power10= ). The regression was due to 'do_client_architecture_support' checking for valid compat modes and finding Power11 to be a valid compat mode for Power10 (it happens even without passing 'max-compat-mode' explicitly). Fix compat-mode issue and regression, by ensuring a future Power processor (with a higher logical_pvr value, eg. P11) cannot be valid compat-mode for an older Power processor (eg. P10) Cc: C=C3=A9dric Le Goater Cc: Daniel Henrique Barboza Cc: Harsh Prateek Bora Cc: Mahesh J Salgaonkar Cc: Madhavan Srinivasan Cc: Nicholas Piggin Reviewed-by: Nicholas Piggin Signed-off-by: Aditya Gupta Tested-by: Amit Machhiwal --- target/ppc/compat.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target/ppc/compat.c b/target/ppc/compat.c index ebef2cccecf3..5b20fd7ef04c 100644 --- a/target/ppc/compat.c +++ b/target/ppc/compat.c @@ -132,6 +132,10 @@ static bool pcc_compat(PowerPCCPUClass *pcc, uint32_t = compat_pvr, /* Outside specified range */ return false; } + if (compat->pvr > pcc->spapr_logical_pvr) { + /* Older CPU cannot support a newer processor's compat mode */ + return false; + } if (!(pcc->pcr_supported & compat->pcr_level)) { /* Not supported by this CPU */ return false; --=20 2.45.2 From nobody Sun Nov 24 13:49:26 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: rxGD1A41thasgsSWRi_F021uGtg-uU1c X-Proofpoint-GUID: dh0jZj1AmKZ3wsHF5tcJ3UEawCRFD1Fd X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-07-31_02,2024-07-30_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 spamscore=0 malwarescore=0 mlxlogscore=999 suspectscore=0 adultscore=0 priorityscore=1501 impostorscore=0 phishscore=0 lowpriorityscore=0 clxscore=1015 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2407310039 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=adityag@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H3=-0.01, RCVD_IN_MSPIKE_WL=-0.01, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1722405106335116600 Add CPU target code to add support for new Power11 Processor. Power11 core is same as Power10, hence reuse functions defined for Power10. Cc: C=C3=A9dric Le Goater Cc: Daniel Henrique Barboza Cc: Fr=C3=A9d=C3=A9ric Barrat Cc: Harsh Prateek Bora Cc: Mahesh J Salgaonkar Cc: Madhavan Srinivasan Cc: Nicholas Piggin Reviewed-by: Nicholas Piggin Signed-off-by: Aditya Gupta Tested-by: Amit Machhiwal --- target/ppc/compat.c | 7 +++++ target/ppc/cpu-models.c | 3 ++ target/ppc/cpu-models.h | 3 ++ target/ppc/cpu.h | 2 ++ target/ppc/cpu_init.c | 60 ++++++++++++++++++++++++++++++++++++++++ target/ppc/cpu_init.h | 8 ++++++ target/ppc/excp_helper.c | 4 +++ 7 files changed, 87 insertions(+) diff --git a/target/ppc/compat.c b/target/ppc/compat.c index 5b20fd7ef04c..0cec1bde9179 100644 --- a/target/ppc/compat.c +++ b/target/ppc/compat.c @@ -100,6 +100,13 @@ static const CompatInfo compat_table[] =3D { .pcr_level =3D PCR_COMPAT_3_10, .max_vthreads =3D 8, }, + { /* POWER11, ISA3.10 */ + .name =3D "power11", + .pvr =3D CPU_POWERPC_LOGICAL_3_10_P11, + .pcr =3D PCR_COMPAT_3_10, + .pcr_level =3D PCR_COMPAT_3_10, + .max_vthreads =3D 8, + }, }; =20 static const CompatInfo *compat_by_pvr(uint32_t pvr) diff --git a/target/ppc/cpu-models.c b/target/ppc/cpu-models.c index f2301b43f78b..ece348178188 100644 --- a/target/ppc/cpu-models.c +++ b/target/ppc/cpu-models.c @@ -734,6 +734,8 @@ "POWER9 v2.2") POWERPC_DEF("power10_v2.0", CPU_POWERPC_POWER10_DD20, POWER= 10, "POWER10 v2.0") + POWERPC_DEF("power11_v2.0", CPU_POWERPC_POWER11_DD20, POWER= 11, + "POWER11_v2.0") #endif /* defined (TARGET_PPC64) */ =20 /*************************************************************************= **/ @@ -909,6 +911,7 @@ PowerPCCPUAlias ppc_cpu_aliases[] =3D { { "power8nvl", "power8nvl_v1.0" }, { "power9", "power9_v2.2" }, { "power10", "power10_v2.0" }, + { "power11", "power11_v2.0" }, #endif =20 /* Generic PowerPCs */ diff --git a/target/ppc/cpu-models.h b/target/ppc/cpu-models.h index 0229ef3a9a5c..72ad31ba50d7 100644 --- a/target/ppc/cpu-models.h +++ b/target/ppc/cpu-models.h @@ -354,6 +354,8 @@ enum { CPU_POWERPC_POWER10_BASE =3D 0x00800000, CPU_POWERPC_POWER10_DD1 =3D 0x00801100, CPU_POWERPC_POWER10_DD20 =3D 0x00801200, + CPU_POWERPC_POWER11_BASE =3D 0x00820000, + CPU_POWERPC_POWER11_DD20 =3D 0x00821200, CPU_POWERPC_970_v22 =3D 0x00390202, CPU_POWERPC_970FX_v10 =3D 0x00391100, CPU_POWERPC_970FX_v20 =3D 0x003C0200, @@ -391,6 +393,7 @@ enum { CPU_POWERPC_LOGICAL_2_07 =3D 0x0F000004, CPU_POWERPC_LOGICAL_3_00 =3D 0x0F000005, CPU_POWERPC_LOGICAL_3_10 =3D 0x0F000006, + CPU_POWERPC_LOGICAL_3_10_P11 =3D 0x0F000007, }; =20 /* System version register (used on MPC 8xxx) = */ diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 752e11204b35..d1d60b4eac55 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -215,6 +215,8 @@ typedef enum powerpc_excp_t { POWERPC_EXCP_POWER9, /* POWER10 exception model */ POWERPC_EXCP_POWER10, + /* POWER11 exception model */ + POWERPC_EXCP_POWER11, } powerpc_excp_t; =20 /*************************************************************************= ****/ diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index c5cd4133ea2f..9cb5dd4596bf 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -6675,6 +6675,66 @@ POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data) pcc->l1_icache_size =3D 0x8000; } =20 +static void init_proc_POWER11(CPUPPCState *env) +{ + init_proc_POWER10(env); +} + +static bool ppc_pvr_match_power11(PowerPCCPUClass *pcc, uint32_t pvr, bool= best) +{ + uint32_t base =3D pvr & CPU_POWERPC_POWER_SERVER_MASK; + uint32_t pcc_base =3D pcc->pvr & CPU_POWERPC_POWER_SERVER_MASK; + + if (!best && (base =3D=3D CPU_POWERPC_POWER11_BASE)) { + return true; + } + + if (base !=3D pcc_base) { + return false; + } + + if ((pvr & 0x0f00) =3D=3D (pcc->pvr & 0x0f00)) { + return true; + } + + return false; +} + +POWERPC_FAMILY(POWER11)(ObjectClass *oc, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(oc); + PowerPCCPUClass *pcc =3D POWERPC_CPU_CLASS(oc); + + dc->fw_name =3D "PowerPC,POWER11"; + dc->desc =3D "POWER11"; + pcc->spapr_logical_pvr =3D CPU_POWERPC_LOGICAL_3_10_P11; + pcc->pvr_match =3D ppc_pvr_match_power11; + pcc->pcr_mask =3D PPC_PCR_MASK_POWER11; + pcc->pcr_supported =3D PPC_PCR_SUPPORTED_POWER11; + pcc->init_proc =3D init_proc_POWER11; + pcc->check_pow =3D check_pow_nocheck; + pcc->check_attn =3D check_attn_hid0_power9; + pcc->insns_flags =3D PPC_INSNS_FLAGS_POWER11; + pcc->insns_flags2 =3D PPC_INSNS_FLAGS2_POWER11; + pcc->msr_mask =3D PPC_MSR_MASK_POWER11; + pcc->lpcr_mask =3D PPC_LPCR_MASK_POWER11; + + pcc->lpcr_pm =3D LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OE= E; + pcc->mmu_model =3D POWERPC_MMU_3_00; +#if !defined(CONFIG_USER_ONLY) + /* segment page size remain the same */ + pcc->hash64_opts =3D &ppc_hash64_opts_POWER7; + pcc->radix_page_info =3D &POWER10_radix_page_info; + pcc->lrg_decr_bits =3D 56; +#endif + pcc->excp_model =3D POWERPC_EXCP_POWER11; + pcc->bus_model =3D PPC_FLAGS_INPUT_POWER9; + pcc->bfd_mach =3D bfd_mach_ppc64; + pcc->flags =3D POWERPC_FLAGS_POWER11; + pcc->l1_dcache_size =3D 0x8000; + pcc->l1_icache_size =3D 0x8000; +} + #if !defined(CONFIG_USER_ONLY) void cpu_ppc_set_vhyp(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp) { diff --git a/target/ppc/cpu_init.h b/target/ppc/cpu_init.h index 7479b59da73b..355d304e38ae 100644 --- a/target/ppc/cpu_init.h +++ b/target/ppc/cpu_init.h @@ -13,6 +13,8 @@ =20 #define PPC_INSNS_FLAGS_POWER10 PPC_INSNS_FLAGS_POWER9 =20 +#define PPC_INSNS_FLAGS_POWER11 PPC_INSNS_FLAGS_POWER10 + #define PPC_INSNS_FLAGS2_POWER_COMMON \ PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | \ PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | \ @@ -25,6 +27,7 @@ PPC_INSNS_FLAGS2_POWER_COMMON | PPC2_TM #define PPC_INSNS_FLAGS2_POWER10 \ PPC_INSNS_FLAGS2_POWER_COMMON | PPC2_ISA310 +#define PPC_INSNS_FLAGS2_POWER11 PPC_INSNS_FLAGS2_POWER10 =20 #define PPC_MSR_MASK_POWER_COMMON \ (1ull << MSR_SF) | \ @@ -49,16 +52,19 @@ PPC_MSR_MASK_POWER_COMMON | (1ull << MSR_TM) #define PPC_MSR_MASK_POWER10 \ PPC_MSR_MASK_POWER_COMMON +#define PPC_MSR_MASK_POWER11 PPC_MSR_MASK_POWER10 =20 #define PPC_PCR_MASK_POWER9 \ PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07 #define PPC_PCR_MASK_POWER10 \ PPC_PCR_MASK_POWER9 | PCR_COMPAT_3_00 +#define PPC_PCR_MASK_POWER11 PPC_PCR_MASK_POWER10 =20 #define PPC_PCR_SUPPORTED_POWER9 \ PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05 #define PPC_PCR_SUPPORTED_POWER10 \ PPC_PCR_SUPPORTED_POWER9 | PCR_COMPAT_3_10 +#define PPC_PCR_SUPPORTED_POWER11 PPC_PCR_SUPPORTED_POWER10 =20 #define PPC_LPCR_MASK_POWER9 = \ LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD | = \ @@ -70,6 +76,7 @@ /* DD2 adds an extra HAIL bit */ #define PPC_LPCR_MASK_POWER10 \ PPC_LPCR_MASK_POWER9 | LPCR_HAIL +#define PPC_LPCR_MASK_POWER11 PPC_LPCR_MASK_POWER10 =20 #define POWERPC_FLAGS_POWER_COMMON \ POWERPC_FLAG_VRE | POWERPC_FLAG_SE | POWERPC_FLAG_BE | \ @@ -80,5 +87,6 @@ POWERPC_FLAGS_POWER_COMMON | POWERPC_FLAG_TM #define POWERPC_FLAGS_POWER10 \ POWERPC_FLAGS_POWER_COMMON | POWERPC_FLAG_BHRB +#define POWERPC_FLAGS_POWER11 POWERPC_FLAGS_POWER10 =20 #endif /* TARGET_PPC_CPU_INIT_H */ diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index f33fc36db2aa..2029144622d8 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -1661,6 +1661,7 @@ static void powerpc_excp(PowerPCCPU *cpu, int excp) case POWERPC_EXCP_POWER8: case POWERPC_EXCP_POWER9: case POWERPC_EXCP_POWER10: + case POWERPC_EXCP_POWER11: powerpc_excp_books(cpu, excp); break; default: @@ -2018,6 +2019,7 @@ static int ppc_next_unmasked_interrupt(CPUPPCState *e= nv) return p8_next_unmasked_interrupt(env); case POWERPC_EXCP_POWER9: case POWERPC_EXCP_POWER10: + case POWERPC_EXCP_POWER11: return p9_next_unmasked_interrupt(env); default: break; @@ -2372,6 +2374,7 @@ static void ppc_deliver_interrupt(CPUPPCState *env, i= nt interrupt) return p8_deliver_interrupt(env, interrupt); case POWERPC_EXCP_POWER9: case POWERPC_EXCP_POWER10: + case POWERPC_EXCP_POWER11: return p9_deliver_interrupt(env, interrupt); default: break; @@ -3163,6 +3166,7 @@ void ppc_cpu_do_transaction_failed(CPUState *cs, hwad= dr physaddr, case POWERPC_EXCP_POWER8: case POWERPC_EXCP_POWER9: case POWERPC_EXCP_POWER10: + case POWERPC_EXCP_POWER11: /* * Machine check codes can be found in processor User Manual or * Linux or skiboot source. --=20 2.45.2 From nobody Sun Nov 24 13:49:26 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: aqH1b_Lc-cXzFzFBeqKP2xFBYc6jBmfZ X-Proofpoint-GUID: 52fbBXElRhoBn14M3ES9DQ5cq7f9amDB X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-07-31_02,2024-07-30_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 clxscore=1015 mlxlogscore=869 phishscore=0 priorityscore=1501 mlxscore=0 impostorscore=0 bulkscore=0 suspectscore=0 malwarescore=0 adultscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2407310039 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=148.163.158.5; envelope-from=adityag@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H3=-0.01, RCVD_IN_MSPIKE_WL=-0.01, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1722405100848116600 Add sPAPR CPU Core definition for Power11 Cc: C=C3=A9dric Le Goater Cc: Daniel Henrique Barboza Cc: David Gibson Cc: Fr=C3=A9d=C3=A9ric Barrat Cc: Harsh Prateek Bora Cc: Mahesh J Salgaonkar Cc: Madhavan Srinivasan Cc: Nicholas Piggin Reviewed-by: Harsh Prateek Bora Reviewed-by: Nicholas Piggin Signed-off-by: Aditya Gupta Tested-by: Amit Machhiwal --- docs/system/ppc/pseries.rst | 17 +++++++++++++---- hw/ppc/spapr_cpu_core.c | 1 + 2 files changed, 14 insertions(+), 4 deletions(-) diff --git a/docs/system/ppc/pseries.rst b/docs/system/ppc/pseries.rst index a876d897b6e4..bbc51aa7fcdb 100644 --- a/docs/system/ppc/pseries.rst +++ b/docs/system/ppc/pseries.rst @@ -14,10 +14,19 @@ virtualization capabilities. Supported devices =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =20 - * Multi processor support for many Power processors generations: POWER7, - POWER7+, POWER8, POWER8NVL, POWER9, and Power10. Support for POWER5+ ex= ists, - but its state is unknown. - * Interrupt Controller, XICS (POWER8) and XIVE (POWER9 and Power10) + * Multi processor support for many Power processors generations: + - POWER7, POWER7+ + - POWER8, POWER8NVL + - POWER9 + - Power10 + - Power11 + - Support for POWER5+ also exists, works with correct kernel/userspace + * Interrupt Controller + - XICS (POWER8) + - XIVE (Supported by below:) + - POWER9 + - Power10 + - Power11 * vPHB PCIe Host bridge. * vscsi and vnet devices, compatible with the same devices available on a PowerVM hypervisor with VIOS managing LPARs. diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c index 56090abcd11a..347a1643ac7f 100644 --- a/hw/ppc/spapr_cpu_core.c +++ b/hw/ppc/spapr_cpu_core.c @@ -411,6 +411,7 @@ static const TypeInfo spapr_cpu_core_type_infos[] =3D { DEFINE_SPAPR_CPU_CORE_TYPE("power9_v2.0"), DEFINE_SPAPR_CPU_CORE_TYPE("power9_v2.2"), DEFINE_SPAPR_CPU_CORE_TYPE("power10_v2.0"), + DEFINE_SPAPR_CPU_CORE_TYPE("power11_v2.0"), #ifdef CONFIG_KVM DEFINE_SPAPR_CPU_CORE_TYPE("host"), #endif --=20 2.45.2