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b=OOuL/SbSoyT2KsDx vMbWH/1QhBh5rQ8PAdEm1TVOFnuSMDjavY687idzMZf4ttK92YiXrNCjhDkfvlON KXsDJSHUB+6dKFCvYmqJy3Pd2NMY1YBYVjbPAnub7gh/BMoNpXs29R6429O3/cO9 fbqD2S7WLcFinUBIVQB1fSHfhu2qA/JtiLplSBSCO6iV+AUsyjyXejO19ATeMobg b3mS4uW/wlcLpspd8ijzyD8u/3lrfxJaA648T+NDBF8uw3ye1DJNSwEBRKzkvMT0 IBKVxa41Y1zBKuV520TzrKEoGDTqrqELSavKO9MQpzJKjB+LcHBFnDeUQ4+ZlDJ0 AmW2aQ== From: Aditya Gupta To: Mahesh J Salgaonkar , Madhavan Srinivasan , Nicholas Piggin , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Harsh Prateek Bora Cc: , , Daniel Henrique Barboza , =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20Barrat?= Subject: [PATCH v6 4/5] target/ppc: Add Power11 DD2.0 processor Date: Wed, 31 Jul 2024 00:53:24 +0530 Message-ID: <20240730192325.669771-5-adityag@linux.ibm.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240730192325.669771-1-adityag@linux.ibm.com> References: <20240730192325.669771-1-adityag@linux.ibm.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-GUID: AVH3ZIAHRcEXKb8SPbp71SgOibjMe9ld X-Proofpoint-ORIG-GUID: LcDzeofjUbWgzSWWBFLVDgJ3dDmHLnE2 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-07-30_15,2024-07-30_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 malwarescore=0 bulkscore=0 priorityscore=1501 impostorscore=0 phishscore=0 mlxlogscore=999 suspectscore=0 lowpriorityscore=0 mlxscore=0 adultscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2407300134 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=148.163.158.5; envelope-from=adityag@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H3=-0.01, RCVD_IN_MSPIKE_WL=-0.01, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1722367503286116600 Add CPU target code to add support for new Power11 Processor. Power11 core is same as Power10, hence reuse functions defined for Power10. Cc: C=C3=A9dric Le Goater Cc: Daniel Henrique Barboza Cc: Fr=C3=A9d=C3=A9ric Barrat Cc: Harsh Prateek Bora Cc: Mahesh J Salgaonkar Cc: Madhavan Srinivasan Cc: Nicholas Piggin Reviewed-by: Nicholas Piggin Signed-off-by: Aditya Gupta --- target/ppc/compat.c | 7 +++++ target/ppc/cpu-models.c | 3 ++ target/ppc/cpu-models.h | 3 ++ target/ppc/cpu.h | 2 ++ target/ppc/cpu_init.c | 60 ++++++++++++++++++++++++++++++++++++++++ target/ppc/cpu_init.h | 8 ++++++ target/ppc/excp_helper.c | 4 +++ 7 files changed, 87 insertions(+) diff --git a/target/ppc/compat.c b/target/ppc/compat.c index 5b20fd7ef04c..0cec1bde9179 100644 --- a/target/ppc/compat.c +++ b/target/ppc/compat.c @@ -100,6 +100,13 @@ static const CompatInfo compat_table[] =3D { .pcr_level =3D PCR_COMPAT_3_10, .max_vthreads =3D 8, }, + { /* POWER11, ISA3.10 */ + .name =3D "power11", + .pvr =3D CPU_POWERPC_LOGICAL_3_10_P11, + .pcr =3D PCR_COMPAT_3_10, + .pcr_level =3D PCR_COMPAT_3_10, + .max_vthreads =3D 8, + }, }; =20 static const CompatInfo *compat_by_pvr(uint32_t pvr) diff --git a/target/ppc/cpu-models.c b/target/ppc/cpu-models.c index f2301b43f78b..ece348178188 100644 --- a/target/ppc/cpu-models.c +++ b/target/ppc/cpu-models.c @@ -734,6 +734,8 @@ "POWER9 v2.2") POWERPC_DEF("power10_v2.0", CPU_POWERPC_POWER10_DD20, POWER= 10, "POWER10 v2.0") + POWERPC_DEF("power11_v2.0", CPU_POWERPC_POWER11_DD20, POWER= 11, + "POWER11_v2.0") #endif /* defined (TARGET_PPC64) */ =20 /*************************************************************************= **/ @@ -909,6 +911,7 @@ PowerPCCPUAlias ppc_cpu_aliases[] =3D { { "power8nvl", "power8nvl_v1.0" }, { "power9", "power9_v2.2" }, { "power10", "power10_v2.0" }, + { "power11", "power11_v2.0" }, #endif =20 /* Generic PowerPCs */ diff --git a/target/ppc/cpu-models.h b/target/ppc/cpu-models.h index 0229ef3a9a5c..72ad31ba50d7 100644 --- a/target/ppc/cpu-models.h +++ b/target/ppc/cpu-models.h @@ -354,6 +354,8 @@ enum { CPU_POWERPC_POWER10_BASE =3D 0x00800000, CPU_POWERPC_POWER10_DD1 =3D 0x00801100, CPU_POWERPC_POWER10_DD20 =3D 0x00801200, + CPU_POWERPC_POWER11_BASE =3D 0x00820000, + CPU_POWERPC_POWER11_DD20 =3D 0x00821200, CPU_POWERPC_970_v22 =3D 0x00390202, CPU_POWERPC_970FX_v10 =3D 0x00391100, CPU_POWERPC_970FX_v20 =3D 0x003C0200, @@ -391,6 +393,7 @@ enum { CPU_POWERPC_LOGICAL_2_07 =3D 0x0F000004, CPU_POWERPC_LOGICAL_3_00 =3D 0x0F000005, CPU_POWERPC_LOGICAL_3_10 =3D 0x0F000006, + CPU_POWERPC_LOGICAL_3_10_P11 =3D 0x0F000007, }; =20 /* System version register (used on MPC 8xxx) = */ diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 752e11204b35..d1d60b4eac55 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -215,6 +215,8 @@ typedef enum powerpc_excp_t { POWERPC_EXCP_POWER9, /* POWER10 exception model */ POWERPC_EXCP_POWER10, + /* POWER11 exception model */ + POWERPC_EXCP_POWER11, } powerpc_excp_t; =20 /*************************************************************************= ****/ diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index c5cd4133ea2f..9cb5dd4596bf 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -6675,6 +6675,66 @@ POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data) pcc->l1_icache_size =3D 0x8000; } =20 +static void init_proc_POWER11(CPUPPCState *env) +{ + init_proc_POWER10(env); +} + +static bool ppc_pvr_match_power11(PowerPCCPUClass *pcc, uint32_t pvr, bool= best) +{ + uint32_t base =3D pvr & CPU_POWERPC_POWER_SERVER_MASK; + uint32_t pcc_base =3D pcc->pvr & CPU_POWERPC_POWER_SERVER_MASK; + + if (!best && (base =3D=3D CPU_POWERPC_POWER11_BASE)) { + return true; + } + + if (base !=3D pcc_base) { + return false; + } + + if ((pvr & 0x0f00) =3D=3D (pcc->pvr & 0x0f00)) { + return true; + } + + return false; +} + +POWERPC_FAMILY(POWER11)(ObjectClass *oc, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(oc); + PowerPCCPUClass *pcc =3D POWERPC_CPU_CLASS(oc); + + dc->fw_name =3D "PowerPC,POWER11"; + dc->desc =3D "POWER11"; + pcc->spapr_logical_pvr =3D CPU_POWERPC_LOGICAL_3_10_P11; + pcc->pvr_match =3D ppc_pvr_match_power11; + pcc->pcr_mask =3D PPC_PCR_MASK_POWER11; + pcc->pcr_supported =3D PPC_PCR_SUPPORTED_POWER11; + pcc->init_proc =3D init_proc_POWER11; + pcc->check_pow =3D check_pow_nocheck; + pcc->check_attn =3D check_attn_hid0_power9; + pcc->insns_flags =3D PPC_INSNS_FLAGS_POWER11; + pcc->insns_flags2 =3D PPC_INSNS_FLAGS2_POWER11; + pcc->msr_mask =3D PPC_MSR_MASK_POWER11; + pcc->lpcr_mask =3D PPC_LPCR_MASK_POWER11; + + pcc->lpcr_pm =3D LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OE= E; + pcc->mmu_model =3D POWERPC_MMU_3_00; +#if !defined(CONFIG_USER_ONLY) + /* segment page size remain the same */ + pcc->hash64_opts =3D &ppc_hash64_opts_POWER7; + pcc->radix_page_info =3D &POWER10_radix_page_info; + pcc->lrg_decr_bits =3D 56; +#endif + pcc->excp_model =3D POWERPC_EXCP_POWER11; + pcc->bus_model =3D PPC_FLAGS_INPUT_POWER9; + pcc->bfd_mach =3D bfd_mach_ppc64; + pcc->flags =3D POWERPC_FLAGS_POWER11; + pcc->l1_dcache_size =3D 0x8000; + pcc->l1_icache_size =3D 0x8000; +} + #if !defined(CONFIG_USER_ONLY) void cpu_ppc_set_vhyp(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp) { diff --git a/target/ppc/cpu_init.h b/target/ppc/cpu_init.h index 7479b59da73b..355d304e38ae 100644 --- a/target/ppc/cpu_init.h +++ b/target/ppc/cpu_init.h @@ -13,6 +13,8 @@ =20 #define PPC_INSNS_FLAGS_POWER10 PPC_INSNS_FLAGS_POWER9 =20 +#define PPC_INSNS_FLAGS_POWER11 PPC_INSNS_FLAGS_POWER10 + #define PPC_INSNS_FLAGS2_POWER_COMMON \ PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | \ PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | \ @@ -25,6 +27,7 @@ PPC_INSNS_FLAGS2_POWER_COMMON | PPC2_TM #define PPC_INSNS_FLAGS2_POWER10 \ PPC_INSNS_FLAGS2_POWER_COMMON | PPC2_ISA310 +#define PPC_INSNS_FLAGS2_POWER11 PPC_INSNS_FLAGS2_POWER10 =20 #define PPC_MSR_MASK_POWER_COMMON \ (1ull << MSR_SF) | \ @@ -49,16 +52,19 @@ PPC_MSR_MASK_POWER_COMMON | (1ull << MSR_TM) #define PPC_MSR_MASK_POWER10 \ PPC_MSR_MASK_POWER_COMMON +#define PPC_MSR_MASK_POWER11 PPC_MSR_MASK_POWER10 =20 #define PPC_PCR_MASK_POWER9 \ PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07 #define PPC_PCR_MASK_POWER10 \ PPC_PCR_MASK_POWER9 | PCR_COMPAT_3_00 +#define PPC_PCR_MASK_POWER11 PPC_PCR_MASK_POWER10 =20 #define PPC_PCR_SUPPORTED_POWER9 \ PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05 #define PPC_PCR_SUPPORTED_POWER10 \ PPC_PCR_SUPPORTED_POWER9 | PCR_COMPAT_3_10 +#define PPC_PCR_SUPPORTED_POWER11 PPC_PCR_SUPPORTED_POWER10 =20 #define PPC_LPCR_MASK_POWER9 = \ LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD | = \ @@ -70,6 +76,7 @@ /* DD2 adds an extra HAIL bit */ #define PPC_LPCR_MASK_POWER10 \ PPC_LPCR_MASK_POWER9 | LPCR_HAIL +#define PPC_LPCR_MASK_POWER11 PPC_LPCR_MASK_POWER10 =20 #define POWERPC_FLAGS_POWER_COMMON \ POWERPC_FLAG_VRE | POWERPC_FLAG_SE | POWERPC_FLAG_BE | \ @@ -80,5 +87,6 @@ POWERPC_FLAGS_POWER_COMMON | POWERPC_FLAG_TM #define POWERPC_FLAGS_POWER10 \ POWERPC_FLAGS_POWER_COMMON | POWERPC_FLAG_BHRB +#define POWERPC_FLAGS_POWER11 POWERPC_FLAGS_POWER10 =20 #endif /* TARGET_PPC_CPU_INIT_H */ diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index f33fc36db2aa..2029144622d8 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -1661,6 +1661,7 @@ static void powerpc_excp(PowerPCCPU *cpu, int excp) case POWERPC_EXCP_POWER8: case POWERPC_EXCP_POWER9: case POWERPC_EXCP_POWER10: + case POWERPC_EXCP_POWER11: powerpc_excp_books(cpu, excp); break; default: @@ -2018,6 +2019,7 @@ static int ppc_next_unmasked_interrupt(CPUPPCState *e= nv) return p8_next_unmasked_interrupt(env); case POWERPC_EXCP_POWER9: case POWERPC_EXCP_POWER10: + case POWERPC_EXCP_POWER11: return p9_next_unmasked_interrupt(env); default: break; @@ -2372,6 +2374,7 @@ static void ppc_deliver_interrupt(CPUPPCState *env, i= nt interrupt) return p8_deliver_interrupt(env, interrupt); case POWERPC_EXCP_POWER9: case POWERPC_EXCP_POWER10: + case POWERPC_EXCP_POWER11: return p9_deliver_interrupt(env, interrupt); default: break; @@ -3163,6 +3166,7 @@ void ppc_cpu_do_transaction_failed(CPUState *cs, hwad= dr physaddr, case POWERPC_EXCP_POWER8: case POWERPC_EXCP_POWER9: case POWERPC_EXCP_POWER10: + case POWERPC_EXCP_POWER11: /* * Machine check codes can be found in processor User Manual or * Linux or skiboot source. --=20 2.45.2