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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-36b36862549sm14194974f8f.106.2024.07.30.02.40.29 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 Jul 2024 02:40:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1722332429; x=1722937229; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=0t3dw23LYO7KaJ6voFBl2V9URgkrKmEjm+VodO24yXE=; b=G1DZrjxEx0hR/Re43a/s3hVE/4zF4zqBb9mujMooXCK2GqfBhjx2wKQBb8fRpcxr3m SNidaAUX3gzplGfLYtKp7rPqlFJlhF4qCQxyrxt+c5ASNQ6lKO3K0IlzUHXVql1zWsQG wBicXxx0X3Ssb8JJsDZpat9+LiVJryk/gefu1L0Eh1LYIuZxqJNszyNP6+5YgcrIliYj b+IfvUjOSyUX+Eqn3WHIyvaGtj2wIuO0gr/RVVF3n3A7fjXVZ37qp9tU9vCqclecN9U7 vdPnXDCjp4ji6QAcK9avj9OZ5eAj2XJLS+3925RAdOrG07HiXHp6PWGZJAmmrvmDkBaC /f2w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1722332429; x=1722937229; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0t3dw23LYO7KaJ6voFBl2V9URgkrKmEjm+VodO24yXE=; b=K3de6EuOEQGwLKlvsi9JPU+NAdtD8NV5a60kfqlc5a3jXSJi7cwgOAc8cj3QcyAep1 FoH45bDCGq2Ks2odR6KIY6yrZx9iKjLgI2+mwGEIOOB2BvL7+6lbdF+i+v/1nL2pT8Vf HbCRGqF5G/+2tSKeh0DRXc881HpdlqraJIS0Q3/ERc3A8c0pUJyC0Ni7e6mlvvsW7u73 3D0aRgxoSdnHJ29Nk2Y4D/IaQCOkY9b9EZ7LJUFls1NKNCynCwVL1Lq6PbkFkQXwsmD7 Hft/uax5RtRW+X3X+aLb0K5QajQJjFhNP7AJQ2Cr7UMgIOljYoPqmlLFMJAOIYYD8Bdp Bf6w== X-Gm-Message-State: AOJu0Yx3UQo1tgypQz1V3XtTbz1U61eIrTcuC9vZpjh/MMTcJ6HXfS8S dEEOH7NReVrV5C2UtjsshtL+j0GhTuXiAGEe6ojxHSp3i09j9Uhdv/ed/WvsDUfQMdWQsT7GLST Z X-Google-Smtp-Source: AGHT+IEnztkOL3KTo7g9KVqtcd7YlezJS/MHpbqNnO5dcvJBMGLWE5IEZyDktzTr6LTM7hO0jpzkJA== X-Received: by 2002:a5d:4c91:0:b0:367:96b9:760a with SMTP id ffacd0b85a97d-36b5d0ae662mr6825401f8f.41.1722332429644; Tue, 30 Jul 2024 02:40:29 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 13/21] target/arm: Fix UMOPA/UMOPS of 16-bit values Date: Tue, 30 Jul 2024 10:40:12 +0100 Message-Id: <20240730094020.2758637-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240730094020.2758637-1-peter.maydell@linaro.org> References: <20240730094020.2758637-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -11 X-Spam_score: -1.2 X-Spam_bar: - X-Spam_report: (-1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, THIS_AD=0.899 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1722332538766116600 Content-Type: text/plain; charset="utf-8" The UMOPA/UMOPS instructions are supposed to multiply unsigned 8 or 16 bit elements and accumulate the products into a 64-bit element. In the Arm ARM pseudocode, this is done with the usual infinite-precision signed arithmetic. However our implementation doesn't quite get it right, because in the DEF_IMOP_64() macro we do: sum +=3D (NTYPE)(n >> 0) * (MTYPE)(m >> 0); where NTYPE and MTYPE are uint16_t or int16_t. In the uint16_t case, the C usual arithmetic conversions mean the values are converted to "int" type and the multiply is done as a 32-bit multiply. This means that if the inputs are, for example, 0xffff and 0xffff then the result is 0xFFFE0001 as an int, which is then promoted to uint64_t for the accumulation into sum; this promotion incorrectly sign extends the multiply. Avoid the incorrect sign extension by casting to int64_t before the multiply, so we do the multiply as 64-bit signed arithmetic, which is a type large enough that the multiply can never overflow into the sign bit. (The equivalent 8-bit operations in DEF_IMOP_32() are fine, because the 8-bit multiplies can never overflow into the sign bit of a 32-bit integer.) Cc: qemu-stable@nongnu.org Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2372 Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20240722172957.1041231-3-peter.maydell@linaro.org --- target/arm/tcg/sme_helper.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/arm/tcg/sme_helper.c b/target/arm/tcg/sme_helper.c index 50bb088d048..3ba826a6ceb 100644 --- a/target/arm/tcg/sme_helper.c +++ b/target/arm/tcg/sme_helper.c @@ -1162,10 +1162,10 @@ static uint64_t NAME(uint64_t n, uint64_t m, uint64= _t a, uint8_t p, bool neg) \ uint64_t sum =3D 0; = \ /* Apply P to N as a mask, making the inactive elements 0. */ = \ n &=3D expand_pred_h(p); = \ - sum +=3D (NTYPE)(n >> 0) * (MTYPE)(m >> 0); = \ - sum +=3D (NTYPE)(n >> 16) * (MTYPE)(m >> 16); = \ - sum +=3D (NTYPE)(n >> 32) * (MTYPE)(m >> 32); = \ - sum +=3D (NTYPE)(n >> 48) * (MTYPE)(m >> 48); = \ + sum +=3D (int64_t)(NTYPE)(n >> 0) * (MTYPE)(m >> 0); = \ + sum +=3D (int64_t)(NTYPE)(n >> 16) * (MTYPE)(m >> 16); = \ + sum +=3D (int64_t)(NTYPE)(n >> 32) * (MTYPE)(m >> 32); = \ + sum +=3D (int64_t)(NTYPE)(n >> 48) * (MTYPE)(m >> 48); = \ return neg ? a - sum : a + sum; = \ } =20 --=20 2.34.1