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Tsirkin" , Marcel Apfelbaum , Richard Henderson , Eduardo Habkost , qemu-devel@nongnu.org Cc: Zhao Liu Subject: [PATCH 4/4] target/i386/cpu: Mask off SGX/SGX_LC feature words for non-PC machine Date: Tue, 30 Jul 2024 12:55:44 +0800 Message-Id: <20240730045544.2516284-5-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240730045544.2516284-1-zhao1.liu@intel.com> References: <20240730045544.2516284-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.14; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -44 X-Spam_score: -4.5 X-Spam_bar: ---- X-Spam_report: (-4.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.125, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1722314468526116600 Content-Type: text/plain; charset="utf-8" Only PC machine supports SGX, so mask off SGX related feature words for non-PC machine (microvm). Signed-off-by: Zhao Liu --- hw/i386/sgx-stub.c | 5 +++++ hw/i386/sgx.c | 8 ++++++++ include/hw/i386/sgx-epc.h | 1 + target/i386/cpu.c | 15 +++++++++++++++ 4 files changed, 29 insertions(+) diff --git a/hw/i386/sgx-stub.c b/hw/i386/sgx-stub.c index 16b1dfd90bb5..38ff75e9f377 100644 --- a/hw/i386/sgx-stub.c +++ b/hw/i386/sgx-stub.c @@ -32,6 +32,11 @@ void pc_machine_init_sgx_epc(PCMachineState *pcms) memset(&pcms->sgx_epc, 0, sizeof(SGXEPCState)); } =20 +bool check_sgx_support(void) +{ + return false; +} + bool sgx_epc_get_section(int section_nr, uint64_t *addr, uint64_t *size) { return true; diff --git a/hw/i386/sgx.c b/hw/i386/sgx.c index 849472a12865..4900dd414a1f 100644 --- a/hw/i386/sgx.c +++ b/hw/i386/sgx.c @@ -266,6 +266,14 @@ void hmp_info_sgx(Monitor *mon, const QDict *qdict) size); } =20 +bool check_sgx_support(void) +{ + if (!object_dynamic_cast(qdev_get_machine(), TYPE_PC_MACHINE)) { + return false; + } + return true; +} + bool sgx_epc_get_section(int section_nr, uint64_t *addr, uint64_t *size) { PCMachineState *pcms =3D diff --git a/include/hw/i386/sgx-epc.h b/include/hw/i386/sgx-epc.h index 3e00efd870c9..41d55da47999 100644 --- a/include/hw/i386/sgx-epc.h +++ b/include/hw/i386/sgx-epc.h @@ -58,6 +58,7 @@ typedef struct SGXEPCState { int nr_sections; } SGXEPCState; =20 +bool check_sgx_support(void); bool sgx_epc_get_section(int section_nr, uint64_t *addr, uint64_t *size); void sgx_epc_build_srat(GArray *table_data); =20 diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 7f55e9ba3ed8..66f9737a117c 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -6103,6 +6103,21 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU *= cpu, FeatureWord w) } break; =20 + case FEAT_7_0_EBX: +#ifndef CONFIG_USER_ONLY + if (!check_sgx_support()) { + unavail =3D CPUID_7_0_EBX_SGX; + } +#endif + break; + case FEAT_7_0_ECX: +#ifndef CONFIG_USER_ONLY + if (!check_sgx_support()) { + unavail =3D CPUID_7_0_ECX_SGX_LC; + } +#endif + break; + default: break; } --=20 2.34.1