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Mon, 29 Jul 2024 10:53:56 -0700 (PDT) From: Deepak Gupta To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, jim.shu@sifive.com, andy.chiu@sifive.com, jesse.huang@sifive.com, kito.cheng@sifive.com Cc: palmer@dabbelt.com, Alistair.Francis@wdc.com, laurent@vivier.eu, bmeng.cn@gmail.com, liwei1518@gmail.com, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, Deepak Gupta Subject: [PATCH v2 21/24] target/riscv: add trace-hooks for each case of sw-check exception Date: Mon, 29 Jul 2024 10:53:23 -0700 Message-ID: <20240729175327.73705-22-debug@rivosinc.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240729175327.73705-1-debug@rivosinc.com> References: <20240729175327.73705-1-debug@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=debug@rivosinc.com; helo=mail-pf1-x42e.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @rivosinc-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1722275857838116600 Content-Type: text/plain; charset="utf-8" Violations to control flow rules setup by zicfilp and zicfiss lead to software check exceptions. To debug and fix such sw check issues in guest , add trace-hooks for each case. Signed-off-by: Jim Shu Signed-off-by: Deepak Gupta --- target/riscv/insn_trans/trans_rvi.c.inc | 1 + target/riscv/op_helper.c | 4 ++++ target/riscv/trace-events | 6 ++++++ target/riscv/translate.c | 2 ++ 4 files changed, 13 insertions(+) diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_tr= ans/trans_rvi.c.inc index ee868c5fcb..66b26cbe8b 100644 --- a/target/riscv/insn_trans/trans_rvi.c.inc +++ b/target/riscv/insn_trans/trans_rvi.c.inc @@ -65,6 +65,7 @@ static bool trans_lpad(DisasContext *ctx, arg_lpad *a) tcg_constant_tl(RISCV_EXCP_SW_CHECK_FCFI_TVAL), tcg_env, offsetof(CPURISCVState, sw_check_code)); generate_exception(ctx, RISCV_EXCP_SW_CHECK); + trace_zicfilp_unaligned_lpad_instr((uint64_t) ctx->base.pc_nex= t); return true; } } diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 54baa3a966..6a54c6c24d 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -24,6 +24,7 @@ #include "exec/exec-all.h" #include "exec/cpu_ldst.h" #include "exec/helper-proto.h" +#include "trace.h" =20 /* Exceptions processing helpers */ G_NORETURN void riscv_raise_exception(CPURISCVState *env, @@ -283,6 +284,8 @@ void helper_cfi_check_landing_pad(CPURISCVState *env, i= nt lbl) * greater than 31 and then shift 12 right */ if (lbl && (lbl !=3D ((env->gpr[xT2] & 0xFFFFFFFF) >> 12))) { + trace_zicfilp_lpad_reg_mismatch(lbl, + (env->gpr[xT2] & 0xFFFFFFFF) >>= 12); env->sw_check_code =3D RISCV_EXCP_SW_CHECK_FCFI_TVAL; riscv_raise_exception(env, RISCV_EXCP_SW_CHECK, GETPC()); } @@ -295,6 +298,7 @@ void helper_sschk_mismatch(CPURISCVState *env, target_u= long rs1, target_ulong ssra) { if (rs1 !=3D ssra) { + trace_zicfiss_sspopchk_reg_mismatch((uint64_t)ssra, (uint64_t) rs1= ); env->sw_check_code =3D RISCV_EXCP_SW_CHECK_BCFI_TVAL; riscv_raise_exception(env, RISCV_EXCP_SW_CHECK, GETPC()); } diff --git a/target/riscv/trace-events b/target/riscv/trace-events index 49ec4d3b7d..842349ecb9 100644 --- a/target/riscv/trace-events +++ b/target/riscv/trace-events @@ -9,3 +9,9 @@ pmpaddr_csr_write(uint64_t mhartid, uint32_t addr_index, ui= nt64_t val) "hart %" =20 mseccfg_csr_read(uint64_t mhartid, uint64_t val) "hart %" PRIu64 ": read m= seccfg, val: 0x%" PRIx64 mseccfg_csr_write(uint64_t mhartid, uint64_t val) "hart %" PRIu64 ": write= mseccfg, val: 0x%" PRIx64 + +# zicfiss/lp +zicfiss_sspopchk_reg_mismatch(uint64_t ssra, uint64_t rs1) "shadow_stack_r= a: 0x%" PRIx64 ", rs1: 0x%" PRIx64 +zicfilp_missing_lpad_instr(uint64_t pc_first) "pc_first: 0x%" PRIx64 +zicfilp_unaligned_lpad_instr(uint64_t pc_next) "pc_next: 0x%" PRIx64 +zicfilp_lpad_reg_mismatch(int lpad_label, int t2_label) "lpad_label: 0x%x,= t2_label: 0x%x" diff --git a/target/riscv/translate.c b/target/riscv/translate.c index ad0f841807..958a1578d4 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -30,6 +30,7 @@ #include "semihosting/semihost.h" =20 #include "internals.h" +#include "trace.h" =20 #define HELPER_H "helper.h" #include "exec/helper-info.c.inc" @@ -1380,6 +1381,7 @@ static void riscv_tr_tb_stop(DisasContextBase *dcbase= , CPUState *cpu) * illegal instruction exception. */ tcg_set_insn_param(cfi_lp_check, 1, tcgv_i32_arg(tcg_constant_i32(= 1))); + trace_zicfilp_missing_lpad_instr((uint64_t) ctx->base.pc_first); } } =20 --=20 2.44.0