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Mon, 29 Jul 2024 08:28:17 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Thomas Huth , Alistair Francis , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 10/14] tests/functional: Convert the riscv_opensbi avocado test into a standalone test Date: Mon, 29 Jul 2024 17:27:10 +0200 Message-ID: <20240729152714.10225-11-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240729152714.10225-1-philmd@linaro.org> References: <20240729152714.10225-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=philmd@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1722266933546116600 From: Thomas Huth The avocado test defined test functions for both, riscv32 and riscv64. Since we can run the whole file with multiple targets in the new framework, we can now consolidate the functions so we have to only define one function per machine now. Signed-off-by: Thomas Huth Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 Message-ID: <20240724175248.1389201-16-thuth@redhat.com> [PMD: Updated MAINTAINERS] Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- MAINTAINERS | 1 + tests/avocado/riscv_opensbi.py | 63 -------------------------- tests/functional/meson.build | 8 ++++ tests/functional/test_riscv_opensbi.py | 36 +++++++++++++++ 4 files changed, 45 insertions(+), 63 deletions(-) delete mode 100644 tests/avocado/riscv_opensbi.py create mode 100755 tests/functional/test_riscv_opensbi.py diff --git a/MAINTAINERS b/MAINTAINERS index a768808a4a..a906218f9d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -337,6 +337,7 @@ F: include/hw/riscv/ F: linux-user/host/riscv32/ F: linux-user/host/riscv64/ F: tests/tcg/riscv64/ +F: tests/functional/test_riscv_opensbi.py =20 RISC-V XThead* extensions M: Christoph Muellner diff --git a/tests/avocado/riscv_opensbi.py b/tests/avocado/riscv_opensbi.py deleted file mode 100644 index bfff9cc3c3..0000000000 --- a/tests/avocado/riscv_opensbi.py +++ /dev/null @@ -1,63 +0,0 @@ -# OpenSBI boot test for RISC-V machines -# -# Copyright (c) 2022, Ventana Micro -# -# This work is licensed under the terms of the GNU GPL, version 2 or -# later. See the COPYING file in the top-level directory. - -from avocado_qemu import QemuSystemTest -from avocado_qemu import wait_for_console_pattern - -class RiscvOpenSBI(QemuSystemTest): - """ - :avocado: tags=3Daccel:tcg - """ - timeout =3D 5 - - def boot_opensbi(self): - self.vm.set_console() - self.vm.launch() - wait_for_console_pattern(self, 'Platform Name') - wait_for_console_pattern(self, 'Boot HART MEDELEG') - - def test_riscv32_spike(self): - """ - :avocado: tags=3Darch:riscv32 - :avocado: tags=3Dmachine:spike - """ - self.boot_opensbi() - - def test_riscv64_spike(self): - """ - :avocado: tags=3Darch:riscv64 - :avocado: tags=3Dmachine:spike - """ - self.boot_opensbi() - - def test_riscv32_sifive_u(self): - """ - :avocado: tags=3Darch:riscv32 - :avocado: tags=3Dmachine:sifive_u - """ - self.boot_opensbi() - - def test_riscv64_sifive_u(self): - """ - :avocado: tags=3Darch:riscv64 - :avocado: tags=3Dmachine:sifive_u - """ - self.boot_opensbi() - - def test_riscv32_virt(self): - """ - :avocado: tags=3Darch:riscv32 - :avocado: tags=3Dmachine:virt - """ - self.boot_opensbi() - - def test_riscv64_virt(self): - """ - :avocado: tags=3Darch:riscv64 - :avocado: tags=3Dmachine:virt - """ - self.boot_opensbi() diff --git a/tests/functional/meson.build b/tests/functional/meson.build index 48a617033e..94ac97ac53 100644 --- a/tests/functional/meson.build +++ b/tests/functional/meson.build @@ -23,6 +23,14 @@ tests_ppc_quick =3D [ 'ppc_74xx', ] =20 +tests_riscv32_quick =3D [ + 'riscv_opensbi', +] + +tests_riscv64_quick =3D [ + 'riscv_opensbi', +] + tests_x86_64_quick =3D [ 'cpu_queries', 'mem_addr_space', diff --git a/tests/functional/test_riscv_opensbi.py b/tests/functional/test= _riscv_opensbi.py new file mode 100755 index 0000000000..d077e40f42 --- /dev/null +++ b/tests/functional/test_riscv_opensbi.py @@ -0,0 +1,36 @@ +#!/usr/bin/env python3 +# +# OpenSBI boot test for RISC-V machines +# +# Copyright (c) 2022, Ventana Micro +# +# This work is licensed under the terms of the GNU GPL, version 2 or +# later. See the COPYING file in the top-level directory. + +from qemu_test import QemuSystemTest +from qemu_test import wait_for_console_pattern + +class RiscvOpenSBI(QemuSystemTest): + + timeout =3D 5 + + def boot_opensbi(self): + self.vm.set_console() + self.vm.launch() + wait_for_console_pattern(self, 'Platform Name') + wait_for_console_pattern(self, 'Boot HART MEDELEG') + + def test_riscv_spike(self): + self.set_machine('spike') + self.boot_opensbi() + + def test_riscv_sifive_u(self): + self.set_machine('sifive_u') + self.boot_opensbi() + + def test_riscv_virt(self): + self.set_machine('virt') + self.boot_opensbi() + +if __name__ =3D=3D '__main__': + QemuSystemTest.main() --=20 2.45.2