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Thu, 25 Jul 2024 16:59:20 -0700 (PDT) From: Nicholas Piggin To: qemu-devel@nongnu.org Cc: Nicholas Piggin , qemu-ppc@nongnu.org, BALATON Zoltan Subject: [PULL 85/96] target/ppc/mmu_common.c: Remove key field from mmu_ctx_t Date: Fri, 26 Jul 2024 09:53:58 +1000 Message-ID: <20240725235410.451624-86-npiggin@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240725235410.451624-1-npiggin@gmail.com> References: <20240725235410.451624-1-npiggin@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=npiggin@gmail.com; helo=mail-pj1-x1030.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1721952498099116600 Content-Type: text/plain; charset="utf-8" From: BALATON Zoltan Pass it as a function parameter and remove it from mmu_ctx_t. Signed-off-by: BALATON Zoltan Reviewed-by: Nicholas Piggin Signed-off-by: Nicholas Piggin --- target/ppc/mmu_common.c | 26 ++++++++++++++------------ 1 file changed, 14 insertions(+), 12 deletions(-) diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c index fe321ab49c..be09c3b1a3 100644 --- a/target/ppc/mmu_common.c +++ b/target/ppc/mmu_common.c @@ -41,7 +41,6 @@ typedef struct { hwaddr raddr; /* Real address */ int prot; /* Protection bits */ - int key; /* Access key */ } mmu_ctx_t; =20 void ppc_store_sdr1(CPUPPCState *env, target_ulong value) @@ -95,7 +94,7 @@ int ppc6xx_tlb_getnum(CPUPPCState *env, target_ulong eadd= r, static int ppc6xx_tlb_check(CPUPPCState *env, mmu_ctx_t *ctx, target_ulong eaddr, MMUAccessType access_type, target_ulong ptem, - bool nx) + bool key, bool nx) { ppc6xx_tlb_t *tlb; target_ulong *pte1p; @@ -140,7 +139,7 @@ static int ppc6xx_tlb_check(CPUPPCState *env, /* Keep the matching PTE information */ best =3D nr; ctx->raddr =3D tlb->pte1; - ctx->prot =3D ppc_hash32_prot(ctx->key, tlb->pte1 & HPTE32_R_PP, n= x); + ctx->prot =3D ppc_hash32_prot(key, tlb->pte1 & HPTE32_R_PP, nx); if (check_prot_access_type(ctx->prot, access_type)) { qemu_log_mask(CPU_LOG_MMU, "PTE access granted !\n"); ret =3D 0; @@ -295,13 +294,14 @@ static int get_bat_6xx_tlb(CPUPPCState *env, mmu_ctx_= t *ctx, } =20 static int mmu6xx_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx, - target_ulong eaddr, hwaddr *hashp, + target_ulong eaddr, + hwaddr *hashp, bool *keyp, MMUAccessType access_type, int type) { PowerPCCPU *cpu =3D env_archcpu(env); hwaddr hash; target_ulong vsid, sr, pgidx, ptem; - bool pr, ds, nx; + bool key, pr, ds, nx; =20 /* First try to find a BAT entry if there are any */ if (env->nb_BATs && get_bat_6xx_tlb(env, ctx, eaddr, access_type) =3D= =3D 0) { @@ -312,7 +312,8 @@ static int mmu6xx_get_physical_address(CPUPPCState *env= , mmu_ctx_t *ctx, pr =3D FIELD_EX64(env->msr, MSR, PR); =20 sr =3D env->sr[eaddr >> 28]; - ctx->key =3D ppc_hash32_key(pr, sr); + key =3D ppc_hash32_key(pr, sr); + *keyp =3D key; ds =3D sr & SR32_T; nx =3D sr & SR32_NX; vsid =3D sr & SR32_VSID; @@ -329,7 +330,7 @@ static int mmu6xx_get_physical_address(CPUPPCState *env= , mmu_ctx_t *ctx, ptem =3D (vsid << 7) | (pgidx >> 10); /* Virtual segment ID | API */ =20 qemu_log_mask(CPU_LOG_MMU, "pte segment: key=3D%d ds %d nx %d vsid " - TARGET_FMT_lx "\n", ctx->key, ds, nx, vsid); + TARGET_FMT_lx "\n", key, ds, nx, vsid); if (!ds) { /* Check if instruction fetch is allowed, if needed */ if (type =3D=3D ACCESS_CODE && nx) { @@ -343,7 +344,7 @@ static int mmu6xx_get_physical_address(CPUPPCState *env= , mmu_ctx_t *ctx, *hashp =3D hash; =20 /* Software TLB search */ - return ppc6xx_tlb_check(env, ctx, eaddr, access_type, ptem, nx); + return ppc6xx_tlb_check(env, ctx, eaddr, access_type, ptem, key, n= x); } =20 /* Direct-store segment : absolutely *BUGGY* for now */ @@ -367,8 +368,8 @@ static int mmu6xx_get_physical_address(CPUPPCState *env= , mmu_ctx_t *ctx, case ACCESS_EXT: /* eciwx or ecowx */ return -4; } - if ((access_type =3D=3D MMU_DATA_STORE || ctx->key !=3D 1) && - (access_type =3D=3D MMU_DATA_LOAD || ctx->key !=3D 0)) { + if ((access_type =3D=3D MMU_DATA_STORE || !key) && + (access_type =3D=3D MMU_DATA_LOAD || key)) { ctx->raddr =3D eaddr; return 2; } @@ -709,6 +710,7 @@ static bool ppc_6xx_xlate(PowerPCCPU *cpu, vaddr eaddr, CPUPPCState *env =3D &cpu->env; mmu_ctx_t ctx; hwaddr hash =3D 0; /* init to 0 to avoid used uninit warning */ + bool key; int type, ret; =20 if (ppc_real_mode_xlate(cpu, eaddr, access_type, raddrp, psizep, protp= )) { @@ -726,7 +728,7 @@ static bool ppc_6xx_xlate(PowerPCCPU *cpu, vaddr eaddr, } =20 ctx.prot =3D 0; - ret =3D mmu6xx_get_physical_address(env, &ctx, eaddr, &hash, + ret =3D mmu6xx_get_physical_address(env, &ctx, eaddr, &hash, &key, access_type, type); if (ret =3D=3D 0) { *raddrp =3D ctx.raddr; @@ -778,7 +780,7 @@ static bool ppc_6xx_xlate(PowerPCCPU *cpu, vaddr eaddr, env->spr[SPR_DMISS] =3D eaddr; env->spr[SPR_DCMP] |=3D 0x80000000; tlb_miss: - env->error_code |=3D ctx.key << 19; + env->error_code |=3D key << 19; env->spr[SPR_HASH1] =3D ppc_hash32_hpt_base(cpu) + get_pteg_offset32(cpu, hash); env->spr[SPR_HASH2] =3D ppc_hash32_hpt_base(cpu) + --=20 2.45.2