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Thu, 25 Jul 2024 16:59:11 -0700 (PDT) From: Nicholas Piggin To: qemu-devel@nongnu.org Cc: Nicholas Piggin , qemu-ppc@nongnu.org, BALATON Zoltan Subject: [PULL 82/96] target/ppc: Add function to get protection key for hash32 MMU Date: Fri, 26 Jul 2024 09:53:55 +1000 Message-ID: <20240725235410.451624-83-npiggin@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240725235410.451624-1-npiggin@gmail.com> References: <20240725235410.451624-1-npiggin@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102f; envelope-from=npiggin@gmail.com; helo=mail-pj1-x102f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1721952289333116600 Content-Type: text/plain; charset="utf-8" From: BALATON Zoltan Add a function to get key bit from SR and use it instead of open coded version. Signed-off-by: BALATON Zoltan Reviewed-by: Nicholas Piggin Signed-off-by: Nicholas Piggin --- target/ppc/mmu-hash32.c | 9 ++++++--- target/ppc/mmu-hash32.h | 5 +++++ target/ppc/mmu_common.c | 3 +-- 3 files changed, 12 insertions(+), 5 deletions(-) diff --git a/target/ppc/mmu-hash32.c b/target/ppc/mmu-hash32.c index 8a446c8a7d..93559447ff 100644 --- a/target/ppc/mmu-hash32.c +++ b/target/ppc/mmu-hash32.c @@ -42,7 +42,7 @@ static int ppc_hash32_pte_prot(int mmu_idx, { unsigned pp, key; =20 - key =3D !!(mmuidx_pr(mmu_idx) ? (sr & SR32_KP) : (sr & SR32_KS)); + key =3D ppc_hash32_key(mmuidx_pr(mmu_idx), sr); pp =3D pte.pte1 & HPTE32_R_PP; =20 return ppc_hash32_prot(key, pp, !!(sr & SR32_NX)); @@ -145,7 +145,6 @@ static bool ppc_hash32_direct_store(PowerPCCPU *cpu, ta= rget_ulong sr, { CPUState *cs =3D CPU(cpu); CPUPPCState *env =3D &cpu->env; - int key =3D !!(mmuidx_pr(mmu_idx) ? (sr & SR32_KP) : (sr & SR32_KS)); =20 qemu_log_mask(CPU_LOG_MMU, "direct store...\n"); =20 @@ -206,7 +205,11 @@ static bool ppc_hash32_direct_store(PowerPCCPU *cpu, t= arget_ulong sr, cpu_abort(cs, "ERROR: insn should not need address translation\n"); } =20 - *prot =3D key ? PAGE_READ | PAGE_WRITE : PAGE_READ; + if (ppc_hash32_key(mmuidx_pr(mmu_idx), sr)) { + *prot =3D PAGE_READ | PAGE_WRITE; + } else { + *prot =3D PAGE_READ; + } if (check_prot_access_type(*prot, access_type)) { *raddr =3D eaddr; return true; diff --git a/target/ppc/mmu-hash32.h b/target/ppc/mmu-hash32.h index bc4eedbecc..5902cf8333 100644 --- a/target/ppc/mmu-hash32.h +++ b/target/ppc/mmu-hash32.h @@ -102,6 +102,11 @@ static inline void ppc_hash32_store_hpte1(PowerPCCPU *= cpu, stl_phys(CPU(cpu)->as, base + pte_offset + HASH_PTE_SIZE_32 / 2, pte1); } =20 +static inline bool ppc_hash32_key(bool pr, target_ulong sr) +{ + return pr ? (sr & SR32_KP) : (sr & SR32_KS); +} + static inline int ppc_hash32_prot(bool key, int pp, bool nx) { int prot; diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c index 339df377e8..1ed2f45ac7 100644 --- a/target/ppc/mmu_common.c +++ b/target/ppc/mmu_common.c @@ -310,8 +310,7 @@ static int mmu6xx_get_physical_address(CPUPPCState *env= , mmu_ctx_t *ctx, pr =3D FIELD_EX64(env->msr, MSR, PR); =20 sr =3D env->sr[eaddr >> 28]; - ctx->key =3D (((sr & 0x20000000) && pr) || - ((sr & 0x40000000) && !pr)) ? 1 : 0; + ctx->key =3D ppc_hash32_key(pr, sr); ds =3D sr & SR32_T; nx =3D sr & SR32_NX; vsid =3D sr & SR32_VSID; --=20 2.45.2