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Thu, 25 Jul 2024 16:59:08 -0700 (PDT) From: Nicholas Piggin To: qemu-devel@nongnu.org Cc: Nicholas Piggin , qemu-ppc@nongnu.org, BALATON Zoltan Subject: [PULL 81/96] target/ppc/mmu_common.c: Remove ptem field from mmu_ctx_t Date: Fri, 26 Jul 2024 09:53:54 +1000 Message-ID: <20240725235410.451624-82-npiggin@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240725235410.451624-1-npiggin@gmail.com> References: <20240725235410.451624-1-npiggin@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=npiggin@gmail.com; helo=mail-pf1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1721952249195116600 Content-Type: text/plain; charset="utf-8" From: BALATON Zoltan Instead of passing around ptem in context use it once in the same function so it can be removed from mmu_ctx_t. Signed-off-by: BALATON Zoltan Reviewed-by: Nicholas Piggin Signed-off-by: Nicholas Piggin --- target/ppc/mmu_common.c | 23 ++++++++++++++--------- 1 file changed, 14 insertions(+), 9 deletions(-) diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c index 784e833ff2..339df377e8 100644 --- a/target/ppc/mmu_common.c +++ b/target/ppc/mmu_common.c @@ -41,7 +41,6 @@ typedef struct { hwaddr raddr; /* Real address */ int prot; /* Protection bits */ - target_ulong ptem; /* Virtual segment ID | API */ int key; /* Access key */ } mmu_ctx_t; =20 @@ -95,16 +94,18 @@ int ppc6xx_tlb_getnum(CPUPPCState *env, target_ulong ea= ddr, =20 static int ppc6xx_tlb_check(CPUPPCState *env, mmu_ctx_t *ctx, target_ulong eaddr, - MMUAccessType access_type, bool nx) + MMUAccessType access_type, target_ulong ptem, + bool nx) { ppc6xx_tlb_t *tlb; target_ulong *pte1p; int nr, best, way, ret; + bool is_code =3D (access_type =3D=3D MMU_INST_FETCH); =20 best =3D -1; ret =3D -1; /* No TLB found */ for (way =3D 0; way < env->nb_ways; way++) { - nr =3D ppc6xx_tlb_getnum(env, eaddr, way, access_type =3D=3D MMU_I= NST_FETCH); + nr =3D ppc6xx_tlb_getnum(env, eaddr, way, is_code); tlb =3D &env->tlb.tlb6[nr]; /* This test "emulates" the PTE index match for hardware TLBs */ if ((eaddr & TARGET_PAGE_MASK) !=3D tlb->EPN) { @@ -124,7 +125,7 @@ static int ppc6xx_tlb_check(CPUPPCState *env, access_type =3D=3D MMU_INST_FETCH ? 'I' : 'D'); /* Check validity and table match */ if (!pte_is_valid(tlb->pte0) || ((tlb->pte0 >> 6) & 1) !=3D 0 || - (tlb->pte0 & PTE_PTEM_MASK) !=3D ctx->ptem) { + (tlb->pte0 & PTE_PTEM_MASK) !=3D ptem) { continue; } /* all matches should have equal RPN, WIMG & PP */ @@ -164,6 +165,10 @@ static int ppc6xx_tlb_check(CPUPPCState *env, } } } + if (ret =3D=3D -1) { + int r =3D is_code ? SPR_ICMP : SPR_DCMP; + env->spr[r] =3D ptem; + } #if defined(DUMP_PAGE_TABLES) if (qemu_loglevel_mask(CPU_LOG_MMU)) { CPUState *cs =3D env_cpu(env); @@ -293,7 +298,7 @@ static int mmu6xx_get_physical_address(CPUPPCState *env= , mmu_ctx_t *ctx, { PowerPCCPU *cpu =3D env_archcpu(env); hwaddr hash; - target_ulong vsid, sr, pgidx; + target_ulong vsid, sr, pgidx, ptem; bool pr, ds, nx; =20 /* First try to find a BAT entry if there are any */ @@ -320,7 +325,7 @@ static int mmu6xx_get_physical_address(CPUPPCState *env= , mmu_ctx_t *ctx, access_type =3D=3D MMU_DATA_STORE, type); pgidx =3D (eaddr & ~SEGMENT_MASK_256M) >> TARGET_PAGE_BITS; hash =3D vsid ^ pgidx; - ctx->ptem =3D (vsid << 7) | (pgidx >> 10); + ptem =3D (vsid << 7) | (pgidx >> 10); /* Virtual segment ID | API */ =20 qemu_log_mask(CPU_LOG_MMU, "pte segment: key=3D%d ds %d nx %d vsid " TARGET_FMT_lx "\n", ctx->key, ds, nx, vsid); @@ -339,7 +344,7 @@ static int mmu6xx_get_physical_address(CPUPPCState *env= , mmu_ctx_t *ctx, /* Initialize real address with an invalid value */ ctx->raddr =3D (hwaddr)-1ULL; /* Software TLB search */ - return ppc6xx_tlb_check(env, ctx, eaddr, access_type, nx); + return ppc6xx_tlb_check(env, ctx, eaddr, access_type, ptem, nx); } =20 /* Direct-store segment : absolutely *BUGGY* for now */ @@ -741,7 +746,7 @@ static bool ppc_6xx_xlate(PowerPCCPU *cpu, vaddr eaddr, cs->exception_index =3D POWERPC_EXCP_IFTLB; env->error_code =3D 1 << 18; env->spr[SPR_IMISS] =3D eaddr; - env->spr[SPR_ICMP] =3D 0x80000000 | ctx.ptem; + env->spr[SPR_ICMP] |=3D 0x80000000; goto tlb_miss; case -2: /* Access rights violation */ @@ -772,7 +777,7 @@ static bool ppc_6xx_xlate(PowerPCCPU *cpu, vaddr eaddr, env->error_code =3D 0; } env->spr[SPR_DMISS] =3D eaddr; - env->spr[SPR_DCMP] =3D 0x80000000 | ctx.ptem; + env->spr[SPR_DCMP] |=3D 0x80000000; tlb_miss: env->error_code |=3D ctx.key << 19; env->spr[SPR_HASH1] =3D ppc_hash32_hpt_base(cpu) + --=20 2.45.2