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Thu, 25 Jul 2024 16:58:52 -0700 (PDT) From: Nicholas Piggin To: qemu-devel@nongnu.org Cc: Nicholas Piggin , qemu-ppc@nongnu.org, BALATON Zoltan Subject: [PULL 76/96] target/ppc/mmu_common.c: Remove nx field from mmu_ctx_t Date: Fri, 26 Jul 2024 09:53:49 +1000 Message-ID: <20240725235410.451624-77-npiggin@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240725235410.451624-1-npiggin@gmail.com> References: <20240725235410.451624-1-npiggin@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=npiggin@gmail.com; helo=mail-pf1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1721952195478116600 Content-Type: text/plain; charset="utf-8" From: BALATON Zoltan Pass it as a parameter instead. Also use named constants instead of hex values when extracting bits from SR. Signed-off-by: BALATON Zoltan Reviewed-by: Nicholas Piggin Signed-off-by: Nicholas Piggin --- target/ppc/mmu_common.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c index c4902b7632..9f402a979d 100644 --- a/target/ppc/mmu_common.c +++ b/target/ppc/mmu_common.c @@ -43,7 +43,6 @@ typedef struct { int prot; /* Protection bits */ target_ulong ptem; /* Virtual segment ID | API */ int key; /* Access key */ - int nx; /* Non-execute area */ } mmu_ctx_t; =20 void ppc_store_sdr1(CPUPPCState *env, target_ulong value) @@ -94,7 +93,7 @@ int ppc6xx_tlb_getnum(CPUPPCState *env, target_ulong eadd= r, =20 static int ppc6xx_tlb_pte_check(mmu_ctx_t *ctx, target_ulong pte0, target_ulong pte1, int pteh, - MMUAccessType access_type) + MMUAccessType access_type, bool nx) { /* Check validity and table match */ if (!pte_is_valid(pte0) || ((pte0 >> 6) & 1) !=3D pteh || @@ -109,7 +108,7 @@ static int ppc6xx_tlb_pte_check(mmu_ctx_t *ctx, target_= ulong pte0, } /* Keep the matching PTE information */ ctx->raddr =3D pte1; - ctx->prot =3D ppc_hash32_prot(ctx->key, pte1 & HPTE32_R_PP, ctx->nx); + ctx->prot =3D ppc_hash32_prot(ctx->key, pte1 & HPTE32_R_PP, nx); if (check_prot_access_type(ctx->prot, access_type)) { qemu_log_mask(CPU_LOG_MMU, "PTE access granted !\n"); return 0; @@ -121,8 +120,9 @@ static int ppc6xx_tlb_pte_check(mmu_ctx_t *ctx, target_= ulong pte0, =20 /* Software driven TLB helpers */ =20 -static int ppc6xx_tlb_check(CPUPPCState *env, mmu_ctx_t *ctx, - target_ulong eaddr, MMUAccessType access_type) +static int ppc6xx_tlb_check(CPUPPCState *env, + mmu_ctx_t *ctx, target_ulong eaddr, + MMUAccessType access_type, bool nx) { ppc6xx_tlb_t *tlb; target_ulong *pte1p; @@ -150,7 +150,7 @@ static int ppc6xx_tlb_check(CPUPPCState *env, mmu_ctx_t= *ctx, access_type =3D=3D MMU_DATA_STORE ? 'S' : 'L', access_type =3D=3D MMU_INST_FETCH ? 'I' : 'D'); switch (ppc6xx_tlb_pte_check(ctx, tlb->pte0, tlb->pte1, - 0, access_type)) { + 0, access_type, nx)) { case -2: /* Access violation */ ret =3D -2; @@ -322,7 +322,7 @@ static int mmu6xx_get_physical_address(CPUPPCState *env= , mmu_ctx_t *ctx, hwaddr hash; target_ulong vsid, sr, pgidx; int ds, target_page_bits; - bool pr; + bool pr, nx; =20 /* First try to find a BAT entry if there are any */ if (env->nb_BATs && get_bat_6xx_tlb(env, ctx, eaddr, access_type) =3D= =3D 0) { @@ -336,8 +336,8 @@ static int mmu6xx_get_physical_address(CPUPPCState *env= , mmu_ctx_t *ctx, ctx->key =3D (((sr & 0x20000000) && pr) || ((sr & 0x40000000) && !pr)) ? 1 : 0; ds =3D sr & 0x80000000 ? 1 : 0; - ctx->nx =3D sr & 0x10000000 ? 1 : 0; - vsid =3D sr & 0x00FFFFFF; + nx =3D sr & SR32_NX; + vsid =3D sr & SR32_VSID; target_page_bits =3D TARGET_PAGE_BITS; qemu_log_mask(CPU_LOG_MMU, "Check segment v=3D" TARGET_FMT_lx " %d " TARGET_FMT_lx @@ -352,10 +352,10 @@ static int mmu6xx_get_physical_address(CPUPPCState *e= nv, mmu_ctx_t *ctx, ctx->ptem =3D (vsid << 7) | (pgidx >> 10); =20 qemu_log_mask(CPU_LOG_MMU, "pte segment: key=3D%d ds %d nx %d vsid " - TARGET_FMT_lx "\n", ctx->key, ds, ctx->nx, vsid); + TARGET_FMT_lx "\n", ctx->key, ds, nx, vsid); if (!ds) { /* Check if instruction fetch is allowed, if needed */ - if (type =3D=3D ACCESS_CODE && ctx->nx) { + if (type =3D=3D ACCESS_CODE && nx) { qemu_log_mask(CPU_LOG_MMU, "No access allowed\n"); return -3; } @@ -368,7 +368,7 @@ static int mmu6xx_get_physical_address(CPUPPCState *env= , mmu_ctx_t *ctx, /* Initialize real address with an invalid value */ ctx->raddr =3D (hwaddr)-1ULL; /* Software TLB search */ - return ppc6xx_tlb_check(env, ctx, eaddr, access_type); + return ppc6xx_tlb_check(env, ctx, eaddr, access_type, nx); } =20 /* Direct-store segment : absolutely *BUGGY* for now */ --=20 2.45.2