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Tue, 23 Jul 2024 07:15:46 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEHaENQtffzWAnK/R1Mi7TVGE5ArkofLyJk7cc2MVrvetHi/JxCaVvbdrCIQ+cGDFJUPwXQEg== X-Received: by 2002:a5d:4005:0:b0:367:9c46:198 with SMTP id ffacd0b85a97d-369bae3a8b6mr8700722f8f.1.1721744145762; Tue, 23 Jul 2024 07:15:45 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Subject: [PULL 05/11] hpet: fix and cleanup persistence of interrupt status Date: Tue, 23 Jul 2024 16:15:23 +0200 Message-ID: <20240723141529.551737-6-pbonzini@redhat.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240723141529.551737-1-pbonzini@redhat.com> References: <20240723141529.551737-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.133, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1721744256505116600 Content-Type: text/plain; charset="utf-8" There are several bugs in the handling of the ISR register: - switching level->edge was not lowering the interrupt and clearing ISR - switching on the enable bit was not raising a level-triggered interrupt if the timer had fired - the timer must be kept running even if not enabled, in order to set the ISR flag, so writes to HPET_TN_CFG must not call hpet_del_timer() Signed-off-by: Paolo Bonzini --- hw/timer/hpet.c | 60 +++++++++++++++++++++++++++++++++---------------- 1 file changed, 41 insertions(+), 19 deletions(-) diff --git a/hw/timer/hpet.c b/hw/timer/hpet.c index 4cb5393c0b5..58073df02b5 100644 --- a/hw/timer/hpet.c +++ b/hw/timer/hpet.c @@ -196,21 +196,31 @@ static void update_irq(struct HPETTimer *timer, int s= et) } s =3D timer->state; mask =3D 1 << timer->tn; - if (!set || !timer_enabled(timer) || !hpet_enabled(timer->state)) { + + if (set && (timer->config & HPET_TN_TYPE_LEVEL)) { + /* + * If HPET_TN_ENABLE bit is 0, "the timer will still operate and + * generate appropriate status bits, but will not cause an interru= pt" + */ + s->isr |=3D mask; + } else { s->isr &=3D ~mask; + } + + if (set && timer_enabled(timer) && hpet_enabled(s)) { + if (timer_fsb_route(timer)) { + address_space_stl_le(&address_space_memory, timer->fsb >> 32, + timer->fsb & 0xffffffff, MEMTXATTRS_UNSPE= CIFIED, + NULL); + } else if (timer->config & HPET_TN_TYPE_LEVEL) { + qemu_irq_raise(s->irqs[route]); + } else { + qemu_irq_pulse(s->irqs[route]); + } + } else { if (!timer_fsb_route(timer)) { qemu_irq_lower(s->irqs[route]); } - } else if (timer_fsb_route(timer)) { - address_space_stl_le(&address_space_memory, timer->fsb >> 32, - timer->fsb & 0xffffffff, MEMTXATTRS_UNSPECIFI= ED, - NULL); - } else if (timer->config & HPET_TN_TYPE_LEVEL) { - s->isr |=3D mask; - qemu_irq_raise(s->irqs[route]); - } else { - s->isr &=3D ~mask; - qemu_irq_pulse(s->irqs[route]); } } =20 @@ -414,8 +424,13 @@ static void hpet_set_timer(HPETTimer *t) =20 static void hpet_del_timer(HPETTimer *t) { + HPETState *s =3D t->state; timer_del(t->qemu_timer); - update_irq(t, 0); + + if (s->isr & (1 << t->tn)) { + /* For level-triggered interrupt, this leaves ISR set but lowers i= rq. */ + update_irq(t, 1); + } } =20 static uint64_t hpet_ram_read(void *opaque, hwaddr addr, @@ -515,20 +530,26 @@ static void hpet_ram_write(void *opaque, hwaddr addr, switch ((addr - 0x100) % 0x20) { case HPET_TN_CFG: trace_hpet_ram_write_tn_cfg(); - if (activating_bit(old_val, new_val, HPET_TN_FSB_ENABLE)) { + if (deactivating_bit(old_val, new_val, HPET_TN_TYPE_LEVEL)) { + /* + * Do this before changing timer->config; otherwise, if + * HPET_TN_FSB is set, update_irq will not lower the qemu_= irq. + */ update_irq(timer, 0); } val =3D hpet_fixup_reg(new_val, old_val, HPET_TN_CFG_WRITE_MAS= K); timer->config =3D (timer->config & 0xffffffff00000000ULL) | va= l; + if (activating_bit(old_val, new_val, HPET_TN_ENABLE) + && (s->isr & (1 << timer_id))) { + update_irq(timer, 1); + } + if (new_val & HPET_TN_32BIT) { timer->cmp =3D (uint32_t)timer->cmp; timer->period =3D (uint32_t)timer->period; } - if (activating_bit(old_val, new_val, HPET_TN_ENABLE) && - hpet_enabled(s)) { + if (hpet_enabled(s)) { hpet_set_timer(timer); - } else if (deactivating_bit(old_val, new_val, HPET_TN_ENABLE))= { - hpet_del_timer(timer); } break; case HPET_TN_CFG + 4: // Interrupt capabilities @@ -606,9 +627,10 @@ static void hpet_ram_write(void *opaque, hwaddr addr, s->hpet_offset =3D ticks_to_ns(s->hpet_counter) - qemu_clock_get_ns(QEMU_= CLOCK_VIRTUAL); for (i =3D 0; i < s->num_timers; i++) { - if ((&s->timer[i])->cmp !=3D ~0ULL) { - hpet_set_timer(&s->timer[i]); + if (timer_enabled(&s->timer[i]) && (s->isr & (1 << i))= ) { + update_irq(&s->timer[i], 1); } + hpet_set_timer(&s->timer[i]); } } else if (deactivating_bit(old_val, new_val, HPET_CFG_ENABLE)= ) { /* Halt main counter and disable interrupt generation. */ --=20 2.45.2