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Tue, 23 Jul 2024 16:30:26 -0700 (PDT) From: Atish Patra Date: Tue, 23 Jul 2024 16:30:04 -0700 Subject: [PATCH v2 07/13] target/riscv: Add counter delegation/configuration support MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240723-counter_delegation-v2-7-c4170a5348ca@rivosinc.com> References: <20240723-counter_delegation-v2-0-c4170a5348ca@rivosinc.com> In-Reply-To: <20240723-counter_delegation-v2-0-c4170a5348ca@rivosinc.com> To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: palmer@dabbelt.com, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, bin.meng@windriver.com, dbarboza@ventanamicro.com, alistair.francis@wdc.com X-Mailer: b4 0.15-dev-13183 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=atishp@rivosinc.com; helo=mail-pj1-x1034.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @rivosinc-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1721777587454116600 From: Kaiwen Xue The Smcdeleg/Ssccfg adds the support for counter delegation via S*indcsr and Ssccfg. It also adds a new shadow CSR scountinhibit and menvcfg enable bit (CDE) to enable this extension and scountovf virtualization. Signed-off-by: Kaiwen Xue Co-developed-by: Atish Patra Signed-off-by: Atish Patra --- target/riscv/csr.c | 302 +++++++++++++++++++++++++++++++++++++++++++++++++= +--- 1 file changed, 290 insertions(+), 12 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index da27ba1b7580..2369a746a285 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -366,6 +366,21 @@ static RISCVException aia_smode32(CPURISCVState *env, = int csrno) return smode32(env, csrno); } =20 +static RISCVException scountinhibit_pred(CPURISCVState *env, int csrno) +{ + RISCVCPU *cpu =3D env_archcpu(env); + + if (!cpu->cfg.ext_ssccfg || !cpu->cfg.ext_smcdeleg) { + return RISCV_EXCP_ILLEGAL_INST; + } + + if (env->virt_enabled) { + return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; + } + + return smode(env, csrno); +} + static bool csrind_extensions_present(CPURISCVState *env) { return riscv_cpu_cfg(env)->ext_smcsrind || riscv_cpu_cfg(env)->ext_ssc= srind; @@ -1190,10 +1205,9 @@ done: return result; } =20 -static RISCVException write_mhpmcounter(CPURISCVState *env, int csrno, - target_ulong val) +static RISCVException riscv_pmu_write_ctr(CPURISCVState *env, target_ulong= val, + uint32_t ctr_idx) { - int ctr_idx =3D csrno - CSR_MCYCLE; PMUCTRState *counter =3D &env->pmu_ctrs[ctr_idx]; uint64_t mhpmctr_val =3D val; =20 @@ -1218,10 +1232,9 @@ static RISCVException write_mhpmcounter(CPURISCVStat= e *env, int csrno, return RISCV_EXCP_NONE; } =20 -static RISCVException write_mhpmcounterh(CPURISCVState *env, int csrno, - target_ulong val) +static RISCVException riscv_pmu_write_ctrh(CPURISCVState *env, target_ulon= g val, + uint32_t ctr_idx) { - int ctr_idx =3D csrno - CSR_MCYCLEH; PMUCTRState *counter =3D &env->pmu_ctrs[ctr_idx]; uint64_t mhpmctr_val =3D counter->mhpmcounter_val; uint64_t mhpmctrh_val =3D val; @@ -1243,6 +1256,20 @@ static RISCVException write_mhpmcounterh(CPURISCVSta= te *env, int csrno, return RISCV_EXCP_NONE; } =20 +static int write_mhpmcounter(CPURISCVState *env, int csrno, target_ulong v= al) +{ + int ctr_idx =3D csrno - CSR_MCYCLE; + + return riscv_pmu_write_ctr(env, val, ctr_idx); +} + +static int write_mhpmcounterh(CPURISCVState *env, int csrno, target_ulong = val) +{ + int ctr_idx =3D csrno - CSR_MCYCLEH; + + return riscv_pmu_write_ctrh(env, val, ctr_idx); +} + RISCVException riscv_pmu_read_ctr(CPURISCVState *env, target_ulong *val, bool upper_half, uint32_t ctr_idx) { @@ -1308,6 +1335,167 @@ static RISCVException read_hpmcounterh(CPURISCVStat= e *env, int csrno, return riscv_pmu_read_ctr(env, val, true, ctr_index); } =20 +static int rmw_cd_mhpmcounter(CPURISCVState *env, int ctr_idx, + target_ulong *val, target_ulong new_val, + target_ulong wr_mask) +{ + if (wr_mask !=3D 0 && wr_mask !=3D -1) { + return -EINVAL; + } + + if (!wr_mask && val) { + riscv_pmu_read_ctr(env, val, false, ctr_idx); + } else if (wr_mask) { + riscv_pmu_write_ctr(env, new_val, ctr_idx); + } else { + return -EINVAL; + } + + return 0; +} + +static int rmw_cd_mhpmcounterh(CPURISCVState *env, int ctr_idx, + target_ulong *val, target_ulong new_val, + target_ulong wr_mask) +{ + if (wr_mask !=3D 0 && wr_mask !=3D -1) { + return -EINVAL; + } + + if (!wr_mask && val) { + riscv_pmu_read_ctr(env, val, true, ctr_idx); + } else if (wr_mask) { + riscv_pmu_write_ctrh(env, new_val, ctr_idx); + } else { + return -EINVAL; + } + + return 0; +} + +static int rmw_cd_mhpmevent(CPURISCVState *env, int evt_index, + target_ulong *val, target_ulong new_val, + target_ulong wr_mask) +{ + uint64_t mhpmevt_val =3D new_val; + + if (wr_mask !=3D 0 && wr_mask !=3D -1) { + return -EINVAL; + } + + if (!wr_mask && val) { + *val =3D env->mhpmevent_val[evt_index]; + if (riscv_cpu_cfg(env)->ext_sscofpmf) { + *val &=3D ~MHPMEVENT_BIT_MINH; + } + } else if (wr_mask) { + wr_mask &=3D ~MHPMEVENT_BIT_MINH; + mhpmevt_val =3D (new_val & wr_mask) | + (env->mhpmevent_val[evt_index] & ~wr_mask); + if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { + mhpmevt_val =3D mhpmevt_val | + ((uint64_t)env->mhpmeventh_val[evt_index] << 32); + } + env->mhpmevent_val[evt_index] =3D mhpmevt_val; + riscv_pmu_update_event_map(env, mhpmevt_val, evt_index); + } else { + return -EINVAL; + } + + return 0; +} + +static int rmw_cd_mhpmeventh(CPURISCVState *env, int evt_index, + target_ulong *val, target_ulong new_val, + target_ulong wr_mask) +{ + uint64_t mhpmevth_val; + uint64_t mhpmevt_val =3D env->mhpmevent_val[evt_index]; + + if (wr_mask !=3D 0 && wr_mask !=3D -1) { + return -EINVAL; + } + + if (!wr_mask && val) { + *val =3D env->mhpmeventh_val[evt_index]; + if (riscv_cpu_cfg(env)->ext_sscofpmf) { + *val &=3D ~MHPMEVENTH_BIT_MINH; + } + } else if (wr_mask) { + wr_mask &=3D ~MHPMEVENTH_BIT_MINH; + env->mhpmeventh_val[evt_index] =3D + (new_val & wr_mask) | (env->mhpmeventh_val[evt_index] & ~wr_ma= sk); + mhpmevth_val =3D env->mhpmeventh_val[evt_index]; + mhpmevt_val =3D mhpmevt_val | (mhpmevth_val << 32); + riscv_pmu_update_event_map(env, mhpmevt_val, evt_index); + } else { + return -EINVAL; + } + + return 0; +} + +static int rmw_cd_ctr_cfg(CPURISCVState *env, int cfg_index, target_ulong = *val, + target_ulong new_val, target_ulong wr_mask) +{ + switch (cfg_index) { + case 0: /* CYCLECFG */ + if (wr_mask) { + wr_mask &=3D ~MCYCLECFG_BIT_MINH; + env->mcyclecfg =3D (new_val & wr_mask) | (env->mcyclecfg & ~wr= _mask); + } else { + *val =3D env->mcyclecfg &=3D ~MHPMEVENTH_BIT_MINH; + } + break; + case 2: /* INSTRETCFG */ + if (wr_mask) { + wr_mask &=3D ~MINSTRETCFG_BIT_MINH; + env->minstretcfg =3D (new_val & wr_mask) | + (env->minstretcfg & ~wr_mask); + } else { + *val =3D env->minstretcfg &=3D ~MHPMEVENTH_BIT_MINH; + } + break; + default: + return -EINVAL; + } + return 0; +} + +static int rmw_cd_ctr_cfgh(CPURISCVState *env, int cfg_index, target_ulong= *val, + target_ulong new_val, target_ulong wr_mask) +{ + + if (riscv_cpu_mxl(env) !=3D MXL_RV32) { + return RISCV_EXCP_ILLEGAL_INST; + } + + switch (cfg_index) { + case 0: /* CYCLECFGH */ + if (wr_mask) { + wr_mask &=3D ~MCYCLECFGH_BIT_MINH; + env->mcyclecfgh =3D (new_val & wr_mask) | + (env->mcyclecfgh & ~wr_mask); + } else { + *val =3D env->mcyclecfgh; + } + break; + case 2: /* INSTRETCFGH */ + if (wr_mask) { + wr_mask &=3D ~MINSTRETCFGH_BIT_MINH; + env->minstretcfgh =3D (new_val & wr_mask) | + (env->minstretcfgh & ~wr_mask); + } else { + *val =3D env->minstretcfgh; + } + break; + default: + return -EINVAL; + } + return 0; +} + + static RISCVException read_scountovf(CPURISCVState *env, int csrno, target_ulong *val) { @@ -1317,6 +1505,14 @@ static RISCVException read_scountovf(CPURISCVState *= env, int csrno, target_ulong *mhpm_evt_val; uint64_t of_bit_mask; =20 + /* Virtualize scountovf for counter delegation */ + if (riscv_cpu_cfg(env)->ext_sscofpmf && + riscv_cpu_cfg(env)->ext_ssccfg && + get_field(env->menvcfg, MENVCFG_CDE) && + env->virt_enabled) { + return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; + } + if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { mhpm_evt_val =3D env->mhpmeventh_val; of_bit_mask =3D MHPMEVENTH_BIT_OF; @@ -2254,11 +2450,70 @@ static int rmw_xireg_cd(CPURISCVState *env, int csr= no, target_ulong isel, target_ulong *val, target_ulong new_val, target_ulong wr_mask) { - if (!riscv_cpu_cfg(env)->ext_smcdeleg) { + int ret =3D -EINVAL; + int ctr_index =3D isel - ISELECT_CD_FIRST; + int isel_hpm_start =3D ISELECT_CD_FIRST + 3; + + if (!riscv_cpu_cfg(env)->ext_smcdeleg || !riscv_cpu_cfg(env)->ext_sscc= fg) { return RISCV_EXCP_ILLEGAL_INST; } - /* TODO: Implement the functionality later */ - return RISCV_EXCP_NONE; + + /* Invalid siselect value for reserved */ + if (ctr_index =3D=3D 1) { + goto done; + } + + /* sireg4 and sireg5 provides access RV32 only CSRs */ + if (((csrno =3D=3D CSR_SIREG5) || (csrno =3D=3D CSR_SIREG4)) && + (riscv_cpu_mxl(env) !=3D MXL_RV32)) { + return RISCV_EXCP_ILLEGAL_INST; + } + + /* Check Sscofpmf dependancy */ + if (!riscv_cpu_cfg(env)->ext_sscofpmf && csrno =3D=3D CSR_SIREG5 && + (isel_hpm_start <=3D isel && isel <=3D ISELECT_CD_LAST)) { + goto done; + } + + /* Check smcntrpmf dependancy */ + if (!riscv_cpu_cfg(env)->ext_smcntrpmf && + (csrno =3D=3D CSR_SIREG2 || csrno =3D=3D CSR_SIREG5) && + (ISELECT_CD_FIRST <=3D isel && isel < isel_hpm_start)) { + goto done; + } + + if (!get_field(env->mcounteren, BIT(ctr_index)) || + !get_field(env->menvcfg, MENVCFG_CDE)) { + goto done; + } + + switch (csrno) { + case CSR_SIREG: + ret =3D rmw_cd_mhpmcounter(env, ctr_index, val, new_val, wr_mask); + break; + case CSR_SIREG4: + ret =3D rmw_cd_mhpmcounterh(env, ctr_index, val, new_val, wr_mask); + break; + case CSR_SIREG2: + if (ctr_index <=3D 2) { + ret =3D rmw_cd_ctr_cfg(env, ctr_index, val, new_val, wr_mask); + } else { + ret =3D rmw_cd_mhpmevent(env, ctr_index, val, new_val, wr_mask= ); + } + break; + case CSR_SIREG5: + if (ctr_index <=3D 2) { + ret =3D rmw_cd_ctr_cfgh(env, ctr_index, val, new_val, wr_mask); + } else { + ret =3D rmw_cd_mhpmeventh(env, ctr_index, val, new_val, wr_mas= k); + } + break; + default: + goto done; + } + +done: + return ret; } =20 /* @@ -2540,6 +2795,21 @@ static RISCVException write_mcountinhibit(CPURISCVSt= ate *env, int csrno, return RISCV_EXCP_NONE; } =20 +static RISCVException read_scountinhibit(CPURISCVState *env, int csrno, + target_ulong *val) +{ + /* S-mode can only access the bits delegated by M-mode */ + *val =3D env->mcountinhibit & env->mcounteren; + return RISCV_EXCP_NONE; +} + +static RISCVException write_scountinhibit(CPURISCVState *env, int csrno, + target_ulong val) +{ + write_mcountinhibit(env, csrno, val & env->mcounteren); + return RISCV_EXCP_NONE; +} + static RISCVException read_mcounteren(CPURISCVState *env, int csrno, target_ulong *val) { @@ -2642,12 +2912,14 @@ static RISCVException write_menvcfg(CPURISCVState *= env, int csrno, target_ulong val) { const RISCVCPUConfig *cfg =3D riscv_cpu_cfg(env); - uint64_t mask =3D MENVCFG_FIOM | MENVCFG_CBIE | MENVCFG_CBCFE | MENVCF= G_CBZE; + uint64_t mask =3D MENVCFG_FIOM | MENVCFG_CBIE | MENVCFG_CBCFE | + MENVCFG_CBZE | MENVCFG_CDE; =20 if (riscv_cpu_mxl(env) =3D=3D MXL_RV64) { mask |=3D (cfg->ext_svpbmt ? MENVCFG_PBMTE : 0) | (cfg->ext_sstc ? MENVCFG_STCE : 0) | - (cfg->ext_svadu ? MENVCFG_ADUE : 0); + (cfg->ext_svadu ? MENVCFG_ADUE : 0) | + (cfg->ext_smcdeleg ? MENVCFG_CDE : 0); } env->menvcfg =3D (env->menvcfg & ~mask) | (val & mask); =20 @@ -2667,7 +2939,8 @@ static RISCVException write_menvcfgh(CPURISCVState *e= nv, int csrno, const RISCVCPUConfig *cfg =3D riscv_cpu_cfg(env); uint64_t mask =3D (cfg->ext_svpbmt ? MENVCFG_PBMTE : 0) | (cfg->ext_sstc ? MENVCFG_STCE : 0) | - (cfg->ext_svadu ? MENVCFG_ADUE : 0); + (cfg->ext_svadu ? MENVCFG_ADUE : 0) | + (cfg->ext_smcdeleg ? MENVCFG_CDE : 0); uint64_t valh =3D (uint64_t)val << 32; =20 env->menvcfg =3D (env->menvcfg & ~mask) | (valh & mask); @@ -5417,6 +5690,11 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { write_sstateen_1_3, .min_priv_ver =3D PRIV_VERSION_1_12_0 }, =20 + /* Supervisor Counter Delegation */ + [CSR_SCOUNTINHIBIT] =3D {"scountinhibit", scountinhibit_pred, + read_scountinhibit, write_scountinhibit, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + /* Supervisor Trap Setup */ [CSR_SSTATUS] =3D { "sstatus", smode, read_sstatus, write_sst= atus, NULL, read_sstatus_i128 = }, --=20 2.34.1