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Tue, 23 Jul 2024 16:30:32 -0700 (PDT) From: Atish Patra Date: Tue, 23 Jul 2024 16:30:08 -0700 Subject: [PATCH v2 11/13] target/riscv: Repurpose the implied rule startergy MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240723-counter_delegation-v2-11-c4170a5348ca@rivosinc.com> References: <20240723-counter_delegation-v2-0-c4170a5348ca@rivosinc.com> In-Reply-To: <20240723-counter_delegation-v2-0-c4170a5348ca@rivosinc.com> To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: palmer@dabbelt.com, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, bin.meng@windriver.com, dbarboza@ventanamicro.com, alistair.francis@wdc.com X-Mailer: b4 0.15-dev-13183 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=atishp@rivosinc.com; helo=mail-pj1-x102e.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @rivosinc-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1721777581574116600 The current infrastructure for implied ISA extension enabling can be used for other cases where a particular ISA is dependant on multiple other ISA extension to enable all the features. Rename the implied rule functions/data structures to accomodate that. Signed-off-by: Atish Patra --- target/riscv/tcg/tcg-cpu.c | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index d78d5960cf30..1c9a87029423 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -40,7 +40,7 @@ static GHashTable *multi_ext_user_opts; static GHashTable *misa_ext_user_opts; =20 -static GHashTable *multi_ext_implied_rules; +static GHashTable *multi_ext_enabling_rules; static GHashTable *misa_ext_implied_rules; =20 static bool cpu_cfg_ext_is_user_set(uint32_t ext_offset) @@ -730,7 +730,7 @@ static void riscv_cpu_validate_profiles(RISCVCPU *cpu) } } =20 -static void riscv_cpu_init_implied_exts_rules(void) +static void riscv_cpu_init_ext_rules(void) { RISCVCPUImpliedExtsRule *rule; #ifndef CONFIG_USER_ONLY @@ -756,14 +756,14 @@ static void riscv_cpu_init_implied_exts_rules(void) #ifndef CONFIG_USER_ONLY rule->enabled =3D bitmap_new(ms->smp.cpus); #endif - g_hash_table_insert(multi_ext_implied_rules, + g_hash_table_insert(multi_ext_enabling_rules, GUINT_TO_POINTER(rule->ext), (gpointer)rule); } =20 initialized =3D true; } =20 -static void cpu_enable_implied_rule(RISCVCPU *cpu, +static void cpu_enable_ext_rule(RISCVCPU *cpu, RISCVCPUImpliedExtsRule *rule) { CPURISCVState *env =3D &cpu->env; @@ -787,7 +787,7 @@ static void cpu_enable_implied_rule(RISCVCPU *cpu, GUINT_TO_POINTER(misa_bits[i]= )); =20 if (ir) { - cpu_enable_implied_rule(cpu, ir); + cpu_enable_ext_rule(cpu, ir); } } } @@ -798,12 +798,12 @@ static void cpu_enable_implied_rule(RISCVCPU *cpu, rule->implied_multi_exts[i] !=3D RISCV_IMPLIED_EXTS_RULE_END;= i++) { cpu_cfg_ext_auto_update(cpu, rule->implied_multi_exts[i], true= ); =20 - ir =3D g_hash_table_lookup(multi_ext_implied_rules, - GUINT_TO_POINTER( - rule->implied_multi_exts[i])); + ir =3D g_hash_table_lookup(multi_ext_enabling_rules, + GUINT_TO_POINTER( + rule->implied_multi_exts[i])); =20 if (ir) { - cpu_enable_implied_rule(cpu, ir); + cpu_enable_ext_rule(cpu, ir); } } =20 @@ -844,7 +844,7 @@ static void cpu_enable_zc_implied_rules(RISCVCPU *cpu) } } =20 -static void riscv_cpu_enable_implied_rules(RISCVCPU *cpu) +static void riscv_cpu_enable_ext_rules(RISCVCPU *cpu) { RISCVCPUImpliedExtsRule *rule; int i; @@ -855,14 +855,14 @@ static void riscv_cpu_enable_implied_rules(RISCVCPU *= cpu) /* Enable the implied MISAs. */ for (i =3D 0; (rule =3D riscv_misa_ext_implied_rules[i]); i++) { if (riscv_has_ext(&cpu->env, rule->ext)) { - cpu_enable_implied_rule(cpu, rule); + cpu_enable_ext_rule(cpu, rule); } } =20 /* Enable the implied extensions. */ for (i =3D 0; (rule =3D riscv_multi_ext_implied_rules[i]); i++) { if (isa_ext_is_enabled(cpu, rule->ext)) { - cpu_enable_implied_rule(cpu, rule); + cpu_enable_ext_rule(cpu, rule); } } } @@ -872,8 +872,8 @@ void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Err= or **errp) CPURISCVState *env =3D &cpu->env; Error *local_err =3D NULL; =20 - riscv_cpu_init_implied_exts_rules(); - riscv_cpu_enable_implied_rules(cpu); + riscv_cpu_init_ext_rules(); + riscv_cpu_enable_ext_rules(cpu); =20 riscv_cpu_validate_misa_priv(env, &local_err); if (local_err !=3D NULL) { @@ -1385,8 +1385,8 @@ static void riscv_tcg_cpu_instance_init(CPUState *cs) misa_ext_implied_rules =3D g_hash_table_new(NULL, g_direct_equal); } =20 - if (!multi_ext_implied_rules) { - multi_ext_implied_rules =3D g_hash_table_new(NULL, g_direct_equal); + if (!multi_ext_enabling_rules) { + multi_ext_enabling_rules =3D g_hash_table_new(NULL, g_direct_equal= ); } =20 riscv_cpu_add_user_properties(obj); --=20 2.34.1