From: Hendrik Wüthrich <whendrik@google.com> The aim of this patch series is to emulate Intel RDT features in order to make testing of the linux Resctrl subsystem possible with Qemu. A branch with the patches applied can be found at: https://github.com/Gray-Colors/Intel_RDT_patches_applied The changes made introduce the following features: * Feature enumeration for Intel RDT allocation. * Feature enumeration for Intel RDT monitoring. * Intel RDT monitoring system interface. * Intel RDT allocation system interface. By adding these features, a barebones implementation most of the RDT state and MSRs is introduced, which can be enabled through qemu command line flags. The features missing for a faithful recreation of RDT are CDP and non-linear MBA throttle, as well as the possibility to configure various values through the command line, as some properties can be different across different machines. For increased ease of use, the correct features should be automatically enabled on machines that support RDT functionality. The missing features mentioned above will be implemented in the following order: * Expand feature set for RDT allocation to include CDP and non-linear MBA throttle * Allow for command line configuration of some values, such as the L3 CBM length * Automatically enable RDT on machines that officially support it. Will NOT be implemented * Tests to simulate interaction with the host by the guest Command line examples assuming entire patch series is applied (This requires a kernel with Resctrl enabled): To emulate Intel RDT features: Currently, it is necessary to force the RDT options on in qemu, as it is not automatically enabled for any machines. An example would be the following: - Skylake-Server,+l3-cmt,+rdt-m,+rdt-a,+mba,+l3-cat,+l2-cat Just enabling RDT in qemu won't really help, though. The following option allows resctrl in the kernel: - Kernel options: rdt=mbmlocal,mbmtotal,cmt,mba,l2cat,l3cat To use Resctrl in the Qemu, please refer to: https://docs.kernel.org/arch/x86/resctrl.html ‪Hendrik Wüthrich (9): Add Intel RDT device to config. Add state for RDT device. Add init and realize funciontality for RDT device. Add RDT functionality Add RDT device interface through MSRs Add CPUID enumeration for RDT Add RDT feature flags. Adjust CPUID level for RDT features Adjust level for RDT on full_cpuid_auto_level hw/i386/Kconfig | 4 + hw/i386/meson.build | 1 + hw/i386/rdt.c | 271 +++++++++++++++++++++++++++ include/hw/i386/rdt.h | 60 ++++++ target/i386/cpu.c | 134 ++++++++++++- target/i386/cpu.h | 26 +++ target/i386/tcg/sysemu/misc_helper.c | 80 ++++++++ 7 files changed, 574 insertions(+), 2 deletions(-) create mode 100644 hw/i386/rdt.c create mode 100644 include/hw/i386/rdt.h -- 2.45.2.1089.g2a221341d9-goog From: ‪Hendrik Wüthrich <whendrik@google.com> Change config to show RDT, add minimal code to the rdt.c module to make sure things still compile. Signed-off-by: Hendrik Wüthrich <whendrik@google.com> --- hw/i386/Kconfig | 4 ++++ hw/i386/meson.build | 1 + hw/i386/rdt.c | 49 +++++++++++++++++++++++++++++++++++++++++++ include/hw/i386/rdt.h | 12 +++++++++++ 4 files changed, 66 insertions(+) create mode 100644 hw/i386/rdt.c create mode 100644 include/hw/i386/rdt.h diff --git a/hw/i386/Kconfig b/hw/i386/Kconfig index XXXXXXX..XXXXXXX 100644 --- a/hw/i386/Kconfig +++ b/hw/i386/Kconfig @@ -XXX,XX +XXX,XX @@ config SGX bool depends on KVM +config RDT + bool + config PC bool imply APPLESMC @@ -XXX,XX +XXX,XX @@ config PC imply QXL imply SEV imply SGX + imply RDT imply TEST_DEVICES imply TPM_CRB imply TPM_TIS_ISA diff --git a/hw/i386/meson.build b/hw/i386/meson.build index XXXXXXX..XXXXXXX 100644 --- a/hw/i386/meson.build +++ b/hw/i386/meson.build @@ -XXX,XX +XXX,XX @@ i386_ss.add(when: 'CONFIG_VMPORT', if_true: files('vmport.c')) i386_ss.add(when: 'CONFIG_VTD', if_true: files('intel_iommu.c')) i386_ss.add(when: 'CONFIG_SGX', if_true: files('sgx-epc.c','sgx.c'), if_false: files('sgx-stub.c')) +i386_ss.add(when: 'CONFIG_RDT', if_true: files('rdt.c')) i386_ss.add(when: 'CONFIG_ACPI', if_true: files('acpi-common.c')) i386_ss.add(when: 'CONFIG_PC', if_true: files( diff --git a/hw/i386/rdt.c b/hw/i386/rdt.c new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/hw/i386/rdt.c @@ -XXX,XX +XXX,XX @@ +#include "qemu/osdep.h" +#include "hw/i386/rdt.h" +#include <stdint.h> +#include "hw/qdev-properties.h" +#include "qemu/typedefs.h" +#include "qom/object.h" +#include "target/i386/cpu.h" +#include "hw/isa/isa.h" + +#define TYPE_RDT "rdt" + +OBJECT_DECLARE_TYPE(RDTState, RDTStateClass, RDT); + +struct RDTState { + ISADevice parent; +}; + +struct RDTStateClass { }; + +OBJECT_DEFINE_TYPE(RDTState, rdt, RDT, ISA_DEVICE); + +static Property rdt_properties[] = { + DEFINE_PROP_END_OF_LIST(), +}; + +static void rdt_init(Object *obj) +{ +} + +static void rdt_realize(DeviceState *dev, Error **errp) +{ +} + +static void rdt_finalize(Object *obj) +{ +} + +static void rdt_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->hotpluggable = false; + dc->desc = "RDT"; + dc->user_creatable = true; + dc->realize = rdt_realize; + + device_class_set_props(dc, rdt_properties); +} + diff --git a/include/hw/i386/rdt.h b/include/hw/i386/rdt.h new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/include/hw/i386/rdt.h @@ -XXX,XX +XXX,XX @@ +#ifndef HW_RDT_H +#define HW_RDT_H + +#include <stdbool.h> +#include <stdint.h> + +typedef struct RDTState RDTState; +typedef struct RDTStateInstance RDTStateInstance; +typedef struct RDTMonitor RDTMonitor; +typedef struct RDTAllocation RDTAllocation; + +#endif -- 2.45.2.1089.g2a221341d9-goog From: ‪Hendrik Wüthrich <whendrik@google.com> Add structures and variables needed to emulate Intel RDT, including module-internal sturctures and state in ArchCPU. No functionality yet. Signed-off-by: Hendrik Wüthrich <whendrik@google.com> --- hw/i386/rdt.c | 33 +++++++++++++++++++++++++++++++++ target/i386/cpu.h | 5 +++++ 2 files changed, 38 insertions(+) diff --git a/hw/i386/rdt.c b/hw/i386/rdt.c index XXXXXXX..XXXXXXX 100644 --- a/hw/i386/rdt.c +++ b/hw/i386/rdt.c @@ -XXX,XX +XXX,XX @@ #include "target/i386/cpu.h" #include "hw/isa/isa.h" +/* Max counts for allocation masks or CBMs. In other words, the size of respective MSRs*/ +#define MAX_L3_MASK_COUNT 128 +#define MAX_L2_MASK_COUNT 48 +#define MAX_MBA_THRTL_COUNT 31 + #define TYPE_RDT "rdt" +#define RDT_NUM_RMID_PROP "rmids" OBJECT_DECLARE_TYPE(RDTState, RDTStateClass, RDT); +struct RDTMonitor { + uint64_t count_local; + uint64_t count_remote; + uint64_t count_l3; +}; + +struct RDTAllocation { + uint32_t active_cos; +}; + +struct RDTStateInstance { + uint32_t active_rmid; + GArray *monitors; + + RDTState *rdtstate; +}; + struct RDTState { ISADevice parent; + + uint32_t rmids; + + GArray *rdtInstances; + GArray *allocations; + + uint32_t msr_L3_ia32_mask_n[MAX_L3_MASK_COUNT]; + uint32_t msr_L2_ia32_mask_n[MAX_L2_MASK_COUNT]; + uint32_t ia32_L2_qos_ext_bw_thrtl_n[MAX_MBA_THRTL_COUNT]; }; struct RDTStateClass { }; @@ -XXX,XX +XXX,XX @@ struct RDTStateClass { }; OBJECT_DEFINE_TYPE(RDTState, rdt, RDT, ISA_DEVICE); static Property rdt_properties[] = { + DEFINE_PROP_UINT32(RDT_NUM_RMID_PROP, RDTState, rmids, 256), DEFINE_PROP_END_OF_LIST(), }; diff --git a/target/i386/cpu.h b/target/i386/cpu.h index XXXXXXX..XXXXXXX 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState { struct kvm_msrs; +struct RDTState; +struct rdtStateInstance; /** * X86CPU: * @env: #CPUX86State @@ -XXX,XX +XXX,XX @@ struct ArchCPU { struct MemoryRegion *cpu_as_root, *cpu_as_mem, *smram; Notifier machine_done; + /* Help the RDT MSRs find the RDT device */ + struct RDTStateInstance *rdt; + struct kvm_msrs *kvm_msr_buf; int32_t node_id; /* NUMA node this CPU belongs to */ -- 2.45.2.1089.g2a221341d9-goog From: ‪Hendrik Wüthrich <whendrik@google.com> Add code to initialize all necessary state for the RDT device. Signed-off-by: Hendrik Wüthrich <whendrik@google.com> --- hw/i386/rdt.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/hw/i386/rdt.c b/hw/i386/rdt.c index XXXXXXX..XXXXXXX 100644 --- a/hw/i386/rdt.c +++ b/hw/i386/rdt.c @@ -XXX,XX +XXX,XX @@ static void rdt_init(Object *obj) static void rdt_realize(DeviceState *dev, Error **errp) { + CPUState *cs = first_cpu; + + RDTState *rdtDev = RDT(dev); + rdtDev->rdtInstances = g_array_new(false, true, sizeof(RDTStateInstance)); + g_array_set_size(rdtDev->rdtInstances, cs->nr_cores); + CPU_FOREACH(cs) { + RDTStateInstance *rdt = &g_array_index(rdtDev->rdtInstances, RDTStateInstance, cs->cpu_index); + + X86CPU *cpu = X86_CPU(cs); + rdt->rdtstate = rdtDev; + cpu->rdt = rdt; + + rdt->monitors = g_array_new(false, true, sizeof(RDTMonitor)); + rdt->rdtstate->allocations = g_array_new(false, true, sizeof(RDTAllocation)); + + g_array_set_size(rdt->monitors, rdtDev->rmids); + g_array_set_size(rdt->rdtstate->allocations, rdtDev->rmids); + } } static void rdt_finalize(Object *obj) { + CPUState *cs; + RDTState *rdt = RDT(obj); + + CPU_FOREACH(cs) { + RDTStateInstance *rdtInstance = &g_array_index(rdt->rdtInstances, RDTStateInstance, cs->cpu_index); + g_array_free(rdtInstance->monitors, true); + g_array_free(rdtInstance->rdtstate->allocations, true); + } + + g_array_free(rdt->rdtInstances, true); } static void rdt_class_init(ObjectClass *klass, void *data) -- 2.45.2.1089.g2a221341d9-goog From: ‪Hendrik Wüthrich <whendrik@google.com> Add RDT code to Associate CLOSID with RMID / set RMID for monitoring, write COS, and read monitoring data. This patch does not add code for the guest to interact through these things with MSRs, only the actual ability for the RDT device to do them. Signed-off-by: Hendrik Wüthrich <whendrik@google.com> --- hw/i386/rdt.c | 124 ++++++++++++++++++++++++++++++++++++++++++ include/hw/i386/rdt.h | 13 +++++ 2 files changed, 137 insertions(+) diff --git a/hw/i386/rdt.c b/hw/i386/rdt.c index XXXXXXX..XXXXXXX 100644 --- a/hw/i386/rdt.c +++ b/hw/i386/rdt.c @@ -XXX,XX +XXX,XX @@ #include "target/i386/cpu.h" #include "hw/isa/isa.h" +/* RDT Monitoring Event Codes */ +#define RDT_EVENT_L3_OCCUPANCY 1 +#define RDT_EVENT_L3_REMOTE_BW 2 +#define RDT_EVENT_L3_LOCAL_BW 3 + /* Max counts for allocation masks or CBMs. In other words, the size of respective MSRs*/ #define MAX_L3_MASK_COUNT 128 #define MAX_L2_MASK_COUNT 48 @@ -XXX,XX +XXX,XX @@ #define TYPE_RDT "rdt" #define RDT_NUM_RMID_PROP "rmids" +#define QM_CTR_Error (1ULL << 63) +#define QM_CTR_Unavailable (1ULL << 62) + OBJECT_DECLARE_TYPE(RDTState, RDTStateClass, RDT); struct RDTMonitor { @@ -XXX,XX +XXX,XX @@ struct RDTState { struct RDTStateClass { }; +bool rdt_associate_rmid_cos(uint64_t msr_ia32_pqr_assoc) { + X86CPU *cpu = X86_CPU(current_cpu); + RDTStateInstance *rdt = cpu->rdt; + RDTAllocation *alloc; + + uint32_t cos_id = (msr_ia32_pqr_assoc & 0xffff0000) >> 16; + uint32_t rmid = msr_ia32_pqr_assoc & 0xffff; + + if (cos_id > MAX_L3_MASK_COUNT || cos_id > MAX_L2_MASK_COUNT || + cos_id > MAX_MBA_THRTL_COUNT || rmid > rdt_max_rmid(rdt)) { + return false; + } + + rdt->active_rmid = rmid; + + alloc = &g_array_index(rdt->rdtstate->allocations, RDTAllocation, rmid); + + alloc->active_cos = cos_id; + + return true; +} + +uint32_t rdt_read_l3_mask(uint32_t pos) +{ + X86CPU *cpu = X86_CPU(current_cpu); + RDTStateInstance *rdt = cpu->rdt; + + uint32_t val = rdt->rdtstate->msr_L3_ia32_mask_n[pos]; + return val; +} + +uint32_t rdt_read_l2_mask(uint32_t pos) +{ + X86CPU *cpu = X86_CPU(current_cpu); + RDTStateInstance *rdt = cpu->rdt; + + uint32_t val = rdt->rdtstate->msr_L2_ia32_mask_n[pos]; + return val; +} + +uint32_t rdt_read_mba_thrtl(uint32_t pos) +{ + X86CPU *cpu = X86_CPU(current_cpu); + RDTStateInstance *rdt = cpu->rdt; + + uint32_t val = rdt->rdtstate->ia32_L2_qos_ext_bw_thrtl_n[pos]; + return val; +} + +void rdt_write_msr_l3_mask(uint32_t pos, uint32_t val) { + X86CPU *cpu = X86_CPU(current_cpu); + RDTStateInstance *rdt = cpu->rdt; + + rdt->rdtstate->msr_L3_ia32_mask_n[pos] = val; +} + +void rdt_write_msr_l2_mask(uint32_t pos, uint32_t val) { + X86CPU *cpu = X86_CPU(current_cpu); + RDTStateInstance *rdt = cpu->rdt; + + rdt->rdtstate->msr_L2_ia32_mask_n[pos] = val; +} + +void rdt_write_mba_thrtl(uint32_t pos, uint32_t val) { + X86CPU *cpu = X86_CPU(current_cpu); + RDTStateInstance *rdt = cpu->rdt; + + rdt->rdtstate->ia32_L2_qos_ext_bw_thrtl_n[pos] = val; +} + +uint32_t rdt_max_rmid(RDTStateInstance *rdt) +{ + RDTState *rdtdev = rdt->rdtstate; + return rdtdev->rmids - 1; +} + +uint64_t rdt_read_event_count(RDTStateInstance *rdtInstance, uint32_t rmid, uint32_t event_id) +{ + CPUState *cs; + RDTMonitor *mon; + RDTState *rdt = rdtInstance->rdtstate; + + uint32_t count_l3 = 0; + uint32_t count_local= 0; + uint32_t count_remote = 0; + + if (!rdt) { + return 0; + } + + CPU_FOREACH(cs) { + rdtInstance = &g_array_index(rdt->rdtInstances, RDTStateInstance, cs->cpu_index); + if (rmid >= rdtInstance->monitors->len) { + return QM_CTR_Error; + } + mon = &g_array_index(rdtInstance->monitors, RDTMonitor, rmid); + count_l3 += mon->count_l3; + count_local += mon->count_local; + count_remote += mon->count_remote; + } + + switch (event_id) { + case RDT_EVENT_L3_OCCUPANCY: + return count_l3 == 0 ? QM_CTR_Unavailable : count_l3; + break; + case RDT_EVENT_L3_REMOTE_BW: + return count_remote == 0 ? QM_CTR_Unavailable : count_remote; + break; + case RDT_EVENT_L3_LOCAL_BW: + return count_local == 0 ? QM_CTR_Unavailable : count_local; + break; + default: + return QM_CTR_Error; + } +} + OBJECT_DEFINE_TYPE(RDTState, rdt, RDT, ISA_DEVICE); static Property rdt_properties[] = { diff --git a/include/hw/i386/rdt.h b/include/hw/i386/rdt.h index XXXXXXX..XXXXXXX 100644 --- a/include/hw/i386/rdt.h +++ b/include/hw/i386/rdt.h @@ -XXX,XX +XXX,XX @@ typedef struct RDTMonitor RDTMonitor; typedef struct RDTAllocation RDTAllocation; #endif +bool rdt_associate_rmid_cos(uint64_t msr_ia32_pqr_assoc); + +void rdt_write_msr_l3_mask(uint32_t pos, uint32_t val); +void rdt_write_msr_l2_mask(uint32_t pos, uint32_t val); +void rdt_write_mba_thrtl(uint32_t pos, uint32_t val); + +uint32_t rdt_read_l3_mask(uint32_t pos); +uint32_t rdt_read_l2_mask(uint32_t pos); +uint32_t rdt_read_mba_thrtl(uint32_t pos); + +uint64_t rdt_read_event_count(RDTStateInstance *rdt, uint32_t rmid, uint32_t event_id); +uint32_t rdt_max_rmid(RDTStateInstance *rdt); + -- 2.45.2.1089.g2a221341d9-goog From: ‪Hendrik Wüthrich <whendrik@google.com> Implement rdmsr and wrmsr for the following MSRs: * MSR_IA32_PQR_ASSOC * MSR_IA32_QM_EVTSEL * MSR_IA32_QM_CTR * IA32_L3_QOS_Mask_n * IA32_L2_QOS_Mask_n * IA32_L2_QoS_Ext_BW_Thrtl_n This allows for the guest to call RDT-internal functions to associate an RMID with a CLOSID / set an active RMID for monitoring, read monitoring data, and set classes of service. Signed-off-by: Hendrik Wüthrich <whendrik@google.com> --- hw/i386/rdt.c | 8 +++ include/hw/i386/rdt.h | 8 ++- target/i386/cpu.h | 14 +++++ target/i386/tcg/sysemu/misc_helper.c | 80 ++++++++++++++++++++++++++++ 4 files changed, 109 insertions(+), 1 deletion(-) diff --git a/hw/i386/rdt.c b/hw/i386/rdt.c index XXXXXXX..XXXXXXX 100644 --- a/hw/i386/rdt.c +++ b/hw/i386/rdt.c @@ -XXX,XX +XXX,XX @@ #define MAX_L2_MASK_COUNT 48 #define MAX_MBA_THRTL_COUNT 31 +#define CPUID_10_1_EDX_COS_MAX MAX_L3_MASK_COUNT +#define CPUID_10_2_EDX_COS_MAX MAX_L2_MASK_COUNT +#define CPUID_10_3_EDX_COS_MAX MAX_MBA_THRTL_COUNT + #define TYPE_RDT "rdt" #define RDT_NUM_RMID_PROP "rmids" @@ -XXX,XX +XXX,XX @@ struct RDTState { struct RDTStateClass { }; +uint32_t rdt_get_cpuid_10_1_edx_cos_max(void) { return CPUID_10_1_EDX_COS_MAX; } +uint32_t rdt_get_cpuid_10_2_edx_cos_max(void) { return CPUID_10_2_EDX_COS_MAX; } +uint32_t rdt_get_cpuid_10_3_edx_cos_max(void) { return CPUID_10_3_EDX_COS_MAX; } + bool rdt_associate_rmid_cos(uint64_t msr_ia32_pqr_assoc) { X86CPU *cpu = X86_CPU(current_cpu); RDTStateInstance *rdt = cpu->rdt; diff --git a/include/hw/i386/rdt.h b/include/hw/i386/rdt.h index XXXXXXX..XXXXXXX 100644 --- a/include/hw/i386/rdt.h +++ b/include/hw/i386/rdt.h @@ -XXX,XX +XXX,XX @@ typedef struct RDTStateInstance RDTStateInstance; typedef struct RDTMonitor RDTMonitor; typedef struct RDTAllocation RDTAllocation; -#endif +uint32_t rdt_get_cpuid_10_1_edx_cos_max(void); + +uint32_t rdt_get_cpuid_10_2_edx_cos_max(void); + +uint32_t rdt_get_cpuid_10_3_edx_cos_max(void); + bool rdt_associate_rmid_cos(uint64_t msr_ia32_pqr_assoc); void rdt_write_msr_l3_mask(uint32_t pos, uint32_t val); @@ -XXX,XX +XXX,XX @@ uint32_t rdt_read_mba_thrtl(uint32_t pos); uint64_t rdt_read_event_count(RDTStateInstance *rdt, uint32_t rmid, uint32_t event_id); uint32_t rdt_max_rmid(RDTStateInstance *rdt); +#endif diff --git a/target/i386/cpu.h b/target/i386/cpu.h index XXXXXXX..XXXXXXX 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -XXX,XX +XXX,XX @@ typedef enum X86Seg { #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490 #define MSR_IA32_VMX_VMFUNC 0x00000491 +#define MSR_IA32_QM_EVTSEL 0x0c8d +#define MSR_IA32_QM_CTR 0x0c8e +#define MSR_IA32_PQR_ASSOC 0x0c8f + +#define MSR_IA32_L3_CBM_BASE 0x0c90 +#define MSR_IA32_L3_MASKS_END 0x0d0f +#define MSR_IA32_L2_CBM_BASE 0x0d10 +#define MSR_IA32_L2_CBM_END 0x0d4f +#define MSR_IA32_L2_QOS_Ext_BW_Thrtl_BASE 0xd50 +#define MSR_IA32_L2_QOS_Ext_BW_Thrtl_END 0xd80 + #define MSR_APIC_START 0x00000800 #define MSR_APIC_END 0x000008ff @@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState { uint64_t msr_ia32_feature_control; uint64_t msr_ia32_sgxlepubkeyhash[4]; + uint64_t msr_ia32_qm_evtsel; + uint64_t msr_ia32_pqr_assoc; + uint64_t msr_fixed_ctr_ctrl; uint64_t msr_global_ctrl; uint64_t msr_global_status; diff --git a/target/i386/tcg/sysemu/misc_helper.c b/target/i386/tcg/sysemu/misc_helper.c index XXXXXXX..XXXXXXX 100644 --- a/target/i386/tcg/sysemu/misc_helper.c +++ b/target/i386/tcg/sysemu/misc_helper.c @@ -XXX,XX +XXX,XX @@ #include "exec/address-spaces.h" #include "exec/exec-all.h" #include "tcg/helper-tcg.h" +#include "hw/i386/rdt.h" #include "hw/i386/apic.h" void helper_outb(CPUX86State *env, uint32_t port, uint32_t data) @@ -XXX,XX +XXX,XX @@ void helper_wrmsr(CPUX86State *env) env->msr_bndcfgs = val; cpu_sync_bndcs_hflags(env); break; + case MSR_IA32_QM_EVTSEL: + env->msr_ia32_qm_evtsel = val; + break; + case MSR_IA32_PQR_ASSOC: + { + env->msr_ia32_pqr_assoc = val; + bool res = rdt_associate_rmid_cos(val); + if (!res) + goto error; + break; + } + case MSR_IA32_L3_CBM_BASE ... MSR_IA32_L3_MASKS_END: + { + uint32_t pos = (uint32_t)env->regs[R_ECX] - MSR_IA32_L3_CBM_BASE; + if (pos >= rdt_get_cpuid_10_1_edx_cos_max()) { + goto error; + } + rdt_write_msr_l3_mask(pos, val); + break; + } + case MSR_IA32_L2_CBM_BASE ... MSR_IA32_L2_CBM_END: + { + uint32_t pos = (uint32_t)env->regs[R_ECX] - MSR_IA32_L2_CBM_BASE; + if (pos >= rdt_get_cpuid_10_2_edx_cos_max()) { + goto error; + } + rdt_write_msr_l2_mask(pos, val); + break; + } + case MSR_IA32_L2_QOS_Ext_BW_Thrtl_BASE ... MSR_IA32_L2_QOS_Ext_BW_Thrtl_END: + { + uint32_t pos = (uint32_t)env->regs[R_ECX] - MSR_IA32_L2_QOS_Ext_BW_Thrtl_BASE; + if (pos >= rdt_get_cpuid_10_3_edx_cos_max()) { + goto error; + } + rdt_write_mba_thrtl(pos, val); + break; + } case MSR_APIC_START ... MSR_APIC_END: { int ret; int index = (uint32_t)env->regs[R_ECX] - MSR_APIC_START; @@ -XXX,XX +XXX,XX @@ void helper_rdmsr(CPUX86State *env) val = (cs->nr_threads * cs->nr_cores) | (cs->nr_cores << 16); break; } + case MSR_IA32_QM_CTR: + val = rdt_read_event_count(x86_cpu->rdt, + (env->msr_ia32_qm_evtsel >> 32) & 0xff, + env->msr_ia32_qm_evtsel & 0xff); + break; + case MSR_IA32_QM_EVTSEL: + val = env->msr_ia32_qm_evtsel; + break; + case MSR_IA32_PQR_ASSOC: + val = env->msr_ia32_pqr_assoc; + break; + case MSR_IA32_L3_CBM_BASE ... MSR_IA32_L3_MASKS_END: + { + uint32_t pos = (uint32_t)env->regs[R_ECX] - MSR_IA32_L3_CBM_BASE; + if (pos >= rdt_get_cpuid_10_1_edx_cos_max()) { + goto error; + } + val = rdt_read_l3_mask(pos); + break; + } + case MSR_IA32_L2_CBM_BASE ... MSR_IA32_L2_CBM_END: + { + uint32_t pos = (uint32_t)env->regs[R_ECX] - MSR_IA32_L2_CBM_BASE; + if (pos >= rdt_get_cpuid_10_2_edx_cos_max()) { + goto error; + } + val = rdt_read_l2_mask(pos); + break; + } + case MSR_IA32_L2_QOS_Ext_BW_Thrtl_BASE ... MSR_IA32_L2_QOS_Ext_BW_Thrtl_END: + { + uint32_t pos = (uint32_t)env->regs[R_ECX] - MSR_IA32_L2_QOS_Ext_BW_Thrtl_BASE; + if (pos >= rdt_get_cpuid_10_3_edx_cos_max()) { + goto error; + } + val = rdt_read_mba_thrtl(pos); + break; + } case MSR_APIC_START ... MSR_APIC_END: { int ret; int index = (uint32_t)env->regs[R_ECX] - MSR_APIC_START; @@ -XXX,XX +XXX,XX @@ void helper_rdmsr(CPUX86State *env) } env->regs[R_EAX] = (uint32_t)(val); env->regs[R_EDX] = (uint32_t)(val >> 32); +return; +error: + raise_exception_err_ra(env, EXCP0D_GPF, 0, GETPC()); } void helper_flush_page(CPUX86State *env, target_ulong addr) -- 2.45.2.1089.g2a221341d9-goog From: ‪Hendrik Wüthrich <whendrik@google.com> Add CPUID enumeration for intel RDT monitoring and allocation, as well as the flags used in the enumeration code. Signed-off-by: Hendrik Wüthrich <whendrik@google.com> --- hw/i386/rdt.c | 29 ++++++++++++++ include/hw/i386/rdt.h | 29 ++++++++++++++ target/i386/cpu.c | 91 +++++++++++++++++++++++++++++++++++++++++++ target/i386/cpu.h | 5 +++ 4 files changed, 154 insertions(+) diff --git a/hw/i386/rdt.c b/hw/i386/rdt.c index XXXXXXX..XXXXXXX 100644 --- a/hw/i386/rdt.c +++ b/hw/i386/rdt.c @@ -XXX,XX +XXX,XX @@ #define MAX_L2_MASK_COUNT 48 #define MAX_MBA_THRTL_COUNT 31 +/* RDT L3 Allocation features */ +#define CPUID_10_1_EAX_CBM_LENGTH 0xf +#define CPUID_10_1_EBX_CBM 0x0 +#define CPUID_10_1_ECX_CDP 0x0 // to enable, it would be (1U << 2) #define CPUID_10_1_EDX_COS_MAX MAX_L3_MASK_COUNT +/* RDT L2 Allocation features*/ +#define CPUID_10_2_EAX_CBM_LENGTH 0xf +#define CPUID_10_2_EBX_CBM 0x0 #define CPUID_10_2_EDX_COS_MAX MAX_L2_MASK_COUNT +/* RDT MBA features */ +#define CPUID_10_3_EAX_THRTL_MAX 89 +#define CPUID_10_3_ECX_LINEAR_RESPONSE (1U << 2) #define CPUID_10_3_EDX_COS_MAX MAX_MBA_THRTL_COUNT #define TYPE_RDT "rdt" @@ -XXX,XX +XXX,XX @@ struct RDTState { struct RDTStateClass { }; +uint32_t rdt_get_cpuid_15_0_edx_l3(void) { return CPUID_15_1_EDX_L3_OCCUPANCY | CPUID_15_1_EDX_L3_TOTAL_BW | CPUID_15_1_EDX_L3_LOCAL_BW; } + +uint32_t rdt_cpuid_15_1_edx_l3_total_bw_enabled(void) { return CPUID_15_1_EDX_L3_TOTAL_BW; } +uint32_t rdt_cpuid_15_1_edx_l3_local_bw_enabled(void) { return CPUID_15_1_EDX_L3_LOCAL_BW; } +uint32_t rdt_cpuid_15_1_edx_l3_occupancy_enabled(void) { return CPUID_15_1_EDX_L3_OCCUPANCY; } + +uint32_t rdt_cpuid_10_0_ebx_l3_cat_enabled(void) { return CPUID_10_0_EBX_L3_CAT; } +uint32_t rdt_cpuid_10_0_ebx_l2_cat_enabled(void) { return CPUID_10_0_EBX_L2_CAT; } +uint32_t rdt_cpuid_10_0_ebx_l2_mba_enabled(void) { return CPUID_10_0_EBX_MBA; } + +uint32_t rdt_get_cpuid_10_1_eax_cbm_length(void) { return CPUID_10_1_EAX_CBM_LENGTH; } +uint32_t rdt_cpuid_10_1_ebx_cbm_enabled(void) { return CPUID_10_1_EBX_CBM; } +uint32_t rdt_cpuid_10_1_ecx_cdp_enabled(void) { return CPUID_10_1_ECX_CDP; } uint32_t rdt_get_cpuid_10_1_edx_cos_max(void) { return CPUID_10_1_EDX_COS_MAX; } + +uint32_t rdt_get_cpuid_10_2_eax_cbm_length(void) { return CPUID_10_2_EAX_CBM_LENGTH; } +uint32_t rdt_cpuid_10_2_ebx_cbm_enabled(void) { return CPUID_10_2_EBX_CBM; } uint32_t rdt_get_cpuid_10_2_edx_cos_max(void) { return CPUID_10_2_EDX_COS_MAX; } + +uint32_t rdt_get_cpuid_10_3_eax_thrtl_max(void) { return CPUID_10_3_EAX_THRTL_MAX; } +uint32_t rdt_cpuid_10_3_eax_linear_response_enabled(void) { return CPUID_10_3_ECX_LINEAR_RESPONSE; } uint32_t rdt_get_cpuid_10_3_edx_cos_max(void) { return CPUID_10_3_EDX_COS_MAX; } bool rdt_associate_rmid_cos(uint64_t msr_ia32_pqr_assoc) { diff --git a/include/hw/i386/rdt.h b/include/hw/i386/rdt.h index XXXXXXX..XXXXXXX 100644 --- a/include/hw/i386/rdt.h +++ b/include/hw/i386/rdt.h @@ -XXX,XX +XXX,XX @@ #include <stdbool.h> #include <stdint.h> +/* RDT L3 Cache Monitoring Technology */ +#define CPUID_15_0_EDX_L3 (1U << 1) +#define CPUID_15_1_EDX_L3_OCCUPANCY (1U << 0) +#define CPUID_15_1_EDX_L3_TOTAL_BW (1U << 1) +#define CPUID_15_1_EDX_L3_LOCAL_BW (1U << 2) + +/* RDT Cache Allocation Technology */ +#define CPUID_10_0_EBX_L3_CAT (1U << 1) +#define CPUID_10_0_EBX_L2_CAT (1U << 2) +#define CPUID_10_0_EBX_MBA (1U << 3) +#define CPUID_10_0_EDX CPUID_10_0_EBX_L3_CAT | CPUID_10_0_EBX_L2_CAT | CPUID_10_0_EBX_MBA + typedef struct RDTState RDTState; typedef struct RDTStateInstance RDTStateInstance; typedef struct RDTMonitor RDTMonitor; typedef struct RDTAllocation RDTAllocation; +uint32_t rdt_get_cpuid_15_0_edx_l3(void); + +uint32_t rdt_cpuid_15_1_edx_l3_total_bw_enabled(void); +uint32_t rdt_cpuid_15_1_edx_l3_local_bw_enabled(void); +uint32_t rdt_cpuid_15_1_edx_l3_occupancy_enabled(void); + +uint32_t rdt_cpuid_10_0_ebx_l3_cat_enabled(void); +uint32_t rdt_cpuid_10_0_ebx_l2_cat_enabled(void); +uint32_t rdt_cpuid_10_0_ebx_l2_mba_enabled(void); + +uint32_t rdt_get_cpuid_10_1_eax_cbm_length(void); +uint32_t rdt_cpuid_10_1_ebx_cbm_enabled(void); +uint32_t rdt_cpuid_10_1_ecx_cdp_enabled(void); uint32_t rdt_get_cpuid_10_1_edx_cos_max(void); +uint32_t rdt_get_cpuid_10_2_eax_cbm_length(void); +uint32_t rdt_cpuid_10_2_ebx_cbm_enabled(void); uint32_t rdt_get_cpuid_10_2_edx_cos_max(void); +uint32_t rdt_get_cpuid_10_3_eax_thrtl_max(void); +uint32_t rdt_cpuid_10_3_eax_linear_response_enabled(void); uint32_t rdt_get_cpuid_10_3_edx_cos_max(void); bool rdt_associate_rmid_cos(uint64_t msr_ia32_pqr_assoc); diff --git a/target/i386/cpu.c b/target/i386/cpu.c index XXXXXXX..XXXXXXX 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -XXX,XX +XXX,XX @@ #include "hw/boards.h" #include "hw/i386/sgx-epc.h" #endif +#include "hw/i386/rdt.h" #include "disas/capstone.h" #include "cpu-internal.h" @@ -XXX,XX +XXX,XX @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, assert(!(*eax & ~0x1f)); *ebx &= 0xffff; /* The count doesn't need to be reliable. */ break; +#ifndef CONFIG_USER_ONLY + case 0xF: + /* Shared Resource Monitoring Enumeration Leaf */ + *eax = 0; + *ebx = 0; + *ecx = 0; + *edx = 0; + if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_PQM)) + break; + assert(cpu->rdt); + /* Non-zero count is ResId */ + switch (count) { + /* Monitoring Resource Type Enumeration */ + case 0: + *edx = env->features[FEAT_RDT_15_0_EDX]; + *ebx = rdt_max_rmid(cpu->rdt); + break; + /* L3 Cache Monitoring Capability Enumeration Data */ + case 1: + /* Upscaling Factor */ + *ebx = 1; + /* MaxRMID */ + *ecx = rdt_max_rmid(cpu->rdt); + /* Set L3 Total BW */ + *edx |= rdt_cpuid_15_1_edx_l3_total_bw_enabled(); + /* Set L3 Local BW */ + *edx |= rdt_cpuid_15_1_edx_l3_local_bw_enabled(); + /* Set L3 Occupancy */ + *edx |= rdt_cpuid_15_1_edx_l3_occupancy_enabled(); + break; + default: + break; + } + break; + case 0x10: + /* Shared Resource Director Technology Allocation Enumeration Leaf */ + *eax = 0; + *ebx = 0; + *ecx = 0; + *edx = 0; + if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_PQE)) + break; + assert(cpu->rdt); + /* Non-zero count is ResId */ + switch (count) { + /* Cache Allocation Technology Available Resource Types */ + case 0: + /* Set L3 CAT */ + *ebx |= rdt_cpuid_10_0_ebx_l3_cat_enabled(); + /* Set L2 CAT */ + *ebx |= rdt_cpuid_10_0_ebx_l2_cat_enabled(); + /* Set MBA */ + *ebx |= rdt_cpuid_10_0_ebx_l2_mba_enabled(); + // *edx = env->features[FEAT_RDT_10_0_EBX]; + break; + case 1: + /* Length of capacity bitmask in -1 notation */ + *eax = rdt_get_cpuid_10_1_eax_cbm_length(); + /* Capability bit mask */ + *ebx = rdt_cpuid_10_1_ebx_cbm_enabled(); + /* Code and Data priotitization */ + *ecx |= rdt_cpuid_10_1_ecx_cdp_enabled(); + /* Support for n COS masks (zero-referenced)*/ + *edx = rdt_get_cpuid_10_1_edx_cos_max(); + break; + case 2: + /* Length of capacity bitmask in -1 notation */ + *eax = rdt_get_cpuid_10_2_eax_cbm_length(); + /* Capability bit mask */ + *ebx = rdt_cpuid_10_2_ebx_cbm_enabled(); + /* Support for n COS masks (zero-referenced)*/ + *edx = rdt_get_cpuid_10_2_edx_cos_max(); + break; + case 3: + /* Max throttling value -1 (89 means 90) */ + *eax = rdt_get_cpuid_10_3_eax_thrtl_max(); + /* Linear response of delay values */ + *ecx = rdt_cpuid_10_3_eax_linear_response_enabled(); + /* Max number of CLOS -1 (15 means 16) */ + *edx = rdt_get_cpuid_10_3_edx_cos_max(); + break; + default: + *eax = 0; + *ebx = 0; + *ecx = 0; + *edx = 0; + break; + } + break; +#endif case 0x1C: if (cpu->enable_pmu && (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR)) { x86_cpu_get_supported_cpuid(0x1C, 0, eax, ebx, ecx, edx); diff --git a/target/i386/cpu.h b/target/i386/cpu.h index XXXXXXX..XXXXXXX 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -XXX,XX +XXX,XX @@ typedef enum FeatureWord { FEAT_XSAVE_XSS_HI, /* CPUID[EAX=0xd,ECX=1].EDX */ FEAT_7_1_EDX, /* CPUID[EAX=7,ECX=1].EDX */ FEAT_7_2_EDX, /* CPUID[EAX=7,ECX=2].EDX */ + FEAT_RDT_15_0_EDX, /* CPUID[EAX=0xf,ECX=0].EDX (RDT CMT/MBM) */ FEATURE_WORDS, } FeatureWord; @@ -XXX,XX +XXX,XX @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU *cpu, FeatureWord w); #define CPUID_7_0_EBX_INVPCID (1U << 10) /* Restricted Transactional Memory */ #define CPUID_7_0_EBX_RTM (1U << 11) +/* Resource Director Technology Monitoring */ +#define CPUID_7_0_EBX_PQM (1U << 12) /* Memory Protection Extension */ #define CPUID_7_0_EBX_MPX (1U << 14) +/* Resource Director Technology Allocation */ +#define CPUID_7_0_EBX_PQE (1U << 15) /* AVX-512 Foundation */ #define CPUID_7_0_EBX_AVX512F (1U << 16) /* AVX-512 Doubleword & Quadword Instruction */ -- 2.45.2.1089.g2a221341d9-goog From: ‪Hendrik Wüthrich <whendrik@google.com> Add RDT features to feature word / TCG. Signed-off-by: Hendrik Wüthrich <whendrik@google.com> --- target/i386/cpu.c | 30 ++++++++++++++++++++++++++++-- target/i386/cpu.h | 2 ++ 2 files changed, 30 insertions(+), 2 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index XXXXXXX..XXXXXXX 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -XXX,XX +XXX,XX @@ void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1, CPUID_7_0_EBX_CLFLUSHOPT | \ CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \ CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_RDSEED | \ - CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_KERNEL_FEATURES) + CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_KERNEL_FEATURES | \ + CPUID_7_0_EBX_PQM | CPUID_7_0_EBX_PQE) /* missing: CPUID_7_0_EBX_HLE CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM */ @@ -XXX,XX +XXX,XX @@ void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1, #define TCG_SGX_12_0_EAX_FEATURES 0 #define TCG_SGX_12_0_EBX_FEATURES 0 #define TCG_SGX_12_1_EAX_FEATURES 0 +#define TCG_RDT_15_0_EDX_FEATURES CPUID_15_0_EDX_L3 #if defined CONFIG_USER_ONLY #define CPUID_8000_0008_EBX_KERNEL_FEATURES (CPUID_8000_0008_EBX_IBPB | \ @@ -XXX,XX +XXX,XX @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = { "fsgsbase", "tsc-adjust", "sgx", "bmi1", "hle", "avx2", NULL, "smep", "bmi2", "erms", "invpcid", "rtm", - NULL, NULL, "mpx", NULL, + "rdt-m", NULL, "mpx", "rdt-a", "avx512f", "avx512dq", "rdseed", "adx", "smap", "avx512ifma", "pcommit", "clflushopt", "clwb", "intel-pt", "avx512pf", "avx512er", @@ -XXX,XX +XXX,XX @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = { }, .tcg_features = TCG_SGX_12_1_EAX_FEATURES, }, + + [FEAT_RDT_10_0_EBX] = { + .type = CPUID_FEATURE_WORD, + .feat_names = { + NULL, "l3-cat", "l2-cat", "mba" + }, + .cpuid = { + .eax = 0x10, + .needs_ecx = true, .ecx = 0, + .reg = R_EBX, + } + }, + [FEAT_RDT_15_0_EDX] = { + .type = CPUID_FEATURE_WORD, + .feat_names = { + [1] = "l3-cmt" + }, + .cpuid = { + .eax = 0xf, + .needs_ecx = true, .ecx = 0, + .reg = R_EDX, + }, + .tcg_features = TCG_RDT_15_0_EDX_FEATURES, + }, }; typedef struct FeatureMask { diff --git a/target/i386/cpu.h b/target/i386/cpu.h index XXXXXXX..XXXXXXX 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -XXX,XX +XXX,XX @@ typedef enum FeatureWord { FEAT_XSAVE_XSS_HI, /* CPUID[EAX=0xd,ECX=1].EDX */ FEAT_7_1_EDX, /* CPUID[EAX=7,ECX=1].EDX */ FEAT_7_2_EDX, /* CPUID[EAX=7,ECX=2].EDX */ + FEAT_RDT_15_0_EBX, /* CPUID[EAX=0xf,ECX=0].EBX (RDT CMT/MBM) */ FEAT_RDT_15_0_EDX, /* CPUID[EAX=0xf,ECX=0].EDX (RDT CMT/MBM) */ + FEAT_RDT_10_0_EBX, /* CPUID[EAX=0x10,ECX=0].EBX (RDT CAT/MBA) */ FEATURE_WORDS, } FeatureWord; -- 2.45.2.1089.g2a221341d9-goog From: ‪Hendrik Wüthrich <whendrik@google.com> Adjust minimum CPUID level if RDT monitoring or allocation features are enabled to ensure that CPUID will return them. Signed-off-by: Hendrik Wüthrich <whendrik@google.com> --- target/i386/cpu.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index XXXXXXX..XXXXXXX 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -XXX,XX +XXX,XX @@ void x86_cpu_expand_features(X86CPU *cpu, Error **errp) if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SGX) { x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x12); } + + /* RDT monitoring requires CPUID[0xF] */ + if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_PQM) { + x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0xF); + } + + /* RDT allocation requires CPUID[0x10] */ + if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_PQE) { + x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x10); + } } /* Set cpuid_*level* based on cpuid_min_*level, if not explicitly set */ -- 2.45.2.1089.g2a221341d9-goog From: ‪Hendrik Wüthrich <whendrik@google.com> Make sure that RDT monitoring and allocation features are included in in full_cpuid_auto_level. Signed-off-by: Hendrik Wüthrich <whendrik@google.com> --- target/i386/cpu.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index XXXXXXX..XXXXXXX 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -XXX,XX +XXX,XX @@ void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1, #else #define TCG_7_0_ECX_RDPID 0 #endif + #define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | \ /* CPUID_7_0_ECX_OSPKE is dynamic */ \ CPUID_7_0_ECX_LA57 | CPUID_7_0_ECX_PKS | CPUID_7_0_ECX_VAES | \ @@ -XXX,XX +XXX,XX @@ void x86_cpu_expand_features(X86CPU *cpu, Error **errp) x86_cpu_adjust_feat_level(cpu, FEAT_C000_0001_EDX); x86_cpu_adjust_feat_level(cpu, FEAT_SVM); x86_cpu_adjust_feat_level(cpu, FEAT_XSAVE); + x86_cpu_adjust_feat_level(cpu, FEAT_RDT_15_0_EDX); + x86_cpu_adjust_feat_level(cpu, FEAT_RDT_10_0_EBX); /* Intel Processor Trace requires CPUID[0x14] */ if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT)) { -- 2.45.2.1089.g2a221341d9-goog From: Hendrik Wüthrich <whendrik@google.com> The aim of this patch series is to emulate Intel RDT features in order to make testing of the linux Resctrl subsystem possible with Qemu. A branch with the patches applied can be found at: https://github.com/Gray-Colors/Intel_RDT_patches_applied The changes made introduce the following features: * Feature enumeration for Intel RDT allocation. * Feature enumeration for Intel RDT monitoring. * Intel RDT monitoring system interface. * Intel RDT allocation system interface. By adding these features, a barebones implementation most of the RDT state and MSRs is introduced, which can be enabled through qemu command line flags. The features missing for a faithful recreation of RDT are CDP and non-linear MBA throttle, as well as the possibility to configure various values through the command line, as some properties can be different across different machines. For increased ease of use, the correct features should be automatically enabled on machines that support RDT functionality. The missing features mentioned above will be implemented in the following order: * Expand feature set for RDT allocation to include CDP and non-linear MBA throttle * Allow for command line configuration of some values, such as the L3 CBM length * Automatically enable RDT on machines that officially support it. Will NOT be implemented * Tests to simulate interaction with the host by the guest Command line examples assuming entire patch series is applied (This requires a kernel with Resctrl enabled): To emulate Intel RDT features: Currently, it is necessary to force the RDT options on in qemu, as it is not automatically enabled for any machines. An example would be the following: - Skylake-Server,+l3-cmt,+rdt-m,+rdt-a,+mba,+l3-cat,+l2-cat Just enabling RDT in qemu won't really help, though. The following option allows resctrl in the kernel: - Kernel options: rdt=mbmlocal,mbmtotal,cmt,mba,l2cat,l3cat To use Resctrl in the Qemu, please refer to: https://docs.kernel.org/arch/x86/resctrl.html V1 -> V2: - Merge the first commits 1 and 2 from V1 (add RDT device, add RDT state) - Fix endif in rdt.h (was not at end of file in some commits) - Apply recommended cosmetic changes - Add license to new files (rdt.c, rdt.h) - Don't add lines until they are actually needed - Change g_arrays holding RDT state to be pointers, as they never change size - Add "i386:" to each commit message, since other patches seemed to do the same - Fix typo in patch 3 (previously 4) title (add RDT functionality) ‪Hendrik Wüthrich (8): i386: Add Intel RDT device and State to config. i386: Add init and realize functionality for RDT device. i386: Add RDT functionality i386: Add RDT device interface through MSRs i386: Add CPUID enumeration for RDT i386: Add RDT feature flags. i386/cpu: Adjust CPUID level for RDT features i386/cpu: Adjust level for RDT on full_cpuid_auto_level hw/i386/Kconfig | 4 + hw/i386/meson.build | 1 + hw/i386/rdt.c | 281 +++++++++++++++++++++++++++ include/hw/i386/rdt.h | 76 ++++++++ target/i386/cpu.c | 106 +++++++++- target/i386/cpu.h | 24 +++ target/i386/tcg/sysemu/misc_helper.c | 84 ++++++++ 7 files changed, 574 insertions(+), 2 deletions(-) create mode 100644 hw/i386/rdt.c create mode 100644 include/hw/i386/rdt.h -- 2.46.0.469.g59c65b2a67-goog From: ‪Hendrik Wüthrich <whendrik@google.com> Change config to show RDT, add minimal code to the rdt.c module to make sure things still compile. Signed-off-by: Hendrik Wüthrich <whendrik@google.com> --- hw/i386/Kconfig | 4 ++ hw/i386/meson.build | 1 + hw/i386/rdt.c | 96 +++++++++++++++++++++++++++++++++++++++++++ include/hw/i386/rdt.h | 25 +++++++++++ target/i386/cpu.h | 3 ++ 5 files changed, 129 insertions(+) create mode 100644 hw/i386/rdt.c create mode 100644 include/hw/i386/rdt.h diff --git a/hw/i386/Kconfig b/hw/i386/Kconfig index XXXXXXX..XXXXXXX 100644 --- a/hw/i386/Kconfig +++ b/hw/i386/Kconfig @@ -XXX,XX +XXX,XX @@ config SGX bool depends on KVM +config RDT + bool + config PC bool imply APPLESMC @@ -XXX,XX +XXX,XX @@ config PC imply QXL imply SEV imply SGX + imply RDT imply TEST_DEVICES imply TPM_CRB imply TPM_TIS_ISA diff --git a/hw/i386/meson.build b/hw/i386/meson.build index XXXXXXX..XXXXXXX 100644 --- a/hw/i386/meson.build +++ b/hw/i386/meson.build @@ -XXX,XX +XXX,XX @@ i386_ss.add(when: 'CONFIG_VMPORT', if_true: files('vmport.c')) i386_ss.add(when: 'CONFIG_VTD', if_true: files('intel_iommu.c')) i386_ss.add(when: 'CONFIG_SGX', if_true: files('sgx-epc.c','sgx.c'), if_false: files('sgx-stub.c')) +i386_ss.add(when: 'CONFIG_RDT', if_true: files('rdt.c')) i386_ss.add(when: 'CONFIG_ACPI', if_true: files('acpi-common.c')) i386_ss.add(when: 'CONFIG_PC', if_true: files( diff --git a/hw/i386/rdt.c b/hw/i386/rdt.c new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/hw/i386/rdt.c @@ -XXX,XX +XXX,XX @@ +/* + * Intel Resource Director Technology (RDT). + * + * Copyright 2024 Google LLC + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ + +#include "hw/i386/rdt.h" +#include "qemu/osdep.h" /* Needs to be included before isa.h* / +#include "hw/isa/isa.h" +#include "hw/qdev-properties.h" +#include "qom/object.h" + +/* Max counts for allocation masks or CBMs. In other words, the size of respective MSRs*/ +#define RDT_MAX_L3_MASK_COUNT 128 +#define RDT_MAX_L2_MASK_COUNT 48 +#define RDT_MAX_MBA_THRTL_COUNT 31 + +#define TYPE_RDT "rdt" +#define RDT_NUM_RMID_PROP "rmids" + +OBJECT_DECLARE_TYPE(RDTState, RDTStateClass, RDT); + +struct RDTMonitor { + uint64_t count_local; + uint64_t count_remote; + uint64_t count_l3; +}; + +struct RDTAllocation { + uint32_t active_cos; +}; + +struct RDTStatePerCore { + uint32_t active_rmid; + GArray *monitors; + + /*Parent RDTState*/ + RDTState *rdtstate; +}; + +/*One instance of RDT-internal state to be shared by all cores*/ +struct RDTState { + ISADevice parent; + + /*Max amount of RMIDs*/ + uint32_t rmids; + + /*Per core state*/ + RDTStatePerCore *rdtInstances; + RDTAllocation *allocations; + + /*RDT Allocation bitmask MSRs*/ + uint32_t msr_L3_ia32_mask_n[RDT_MAX_L3_MASK_COUNT]; + uint32_t msr_L2_ia32_mask_n[RDT_MAX_L2_MASK_COUNT]; + uint32_t ia32_L2_qos_ext_bw_thrtl_n[RDT_MAX_MBA_THRTL_COUNT]; +}; + +struct RDTStateClass { +}; + +OBJECT_DEFINE_TYPE(RDTState, rdt, RDT, ISA_DEVICE); + +static Property rdt_properties[] = { + DEFINE_PROP_UINT32(RDT_NUM_RMID_PROP, RDTState, rmids, 256), + DEFINE_PROP_END_OF_LIST(), +}; + +static void rdt_init(Object *obj) +{ +} + +static void rdt_finalize(Object *obj) +{ +} + +static void rdt_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->hotpluggable = false; + dc->desc = "RDT"; + dc->user_creatable = true; + + device_class_set_props(dc, rdt_properties); +} + diff --git a/include/hw/i386/rdt.h b/include/hw/i386/rdt.h new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/include/hw/i386/rdt.h @@ -XXX,XX +XXX,XX @@ +/* + * Intel Resource Director Technology (RDT). + * + * Copyright 2024 Google LLC + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ + +#ifndef HW_RDT_H +#define HW_RDT_H + +typedef struct RDTState RDTState; +typedef struct RDTStatePerCore RDTStatePerCore; +typedef struct RDTMonitor RDTMonitor; +typedef struct RDTAllocation RDTAllocation; + +#endif diff --git a/target/i386/cpu.h b/target/i386/cpu.h index XXXXXXX..XXXXXXX 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -XXX,XX +XXX,XX @@ struct ArchCPU { struct MemoryRegion *cpu_as_root, *cpu_as_mem, *smram; Notifier machine_done; + /* Help the RDT MSRs find the RDT device */ + struct RDTStatePerCore *rdt; + struct kvm_msrs *kvm_msr_buf; int32_t node_id; /* NUMA node this CPU belongs to */ -- 2.46.0.469.g59c65b2a67-goog From: ‪Hendrik Wüthrich <whendrik@google.com> Add code to initialize all necessary state for the RDT device. Signed-off-by: Hendrik Wüthrich <whendrik@google.com> --- hw/i386/rdt.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/hw/i386/rdt.c b/hw/i386/rdt.c index XXXXXXX..XXXXXXX 100644 --- a/hw/i386/rdt.c +++ b/hw/i386/rdt.c @@ -XXX,XX +XXX,XX @@ #include "hw/isa/isa.h" #include "hw/qdev-properties.h" #include "qom/object.h" +#include "target/i386/cpu.h" /* Max counts for allocation masks or CBMs. In other words, the size of respective MSRs*/ #define RDT_MAX_L3_MASK_COUNT 128 @@ -XXX,XX +XXX,XX @@ static void rdt_init(Object *obj) { } +static void rdt_realize(DeviceState *dev, Error **errp) +{ + CPUState *cs = first_cpu; + RDTState *rdtDev = RDT(dev); + + rdtDev->rdtInstances = g_malloc(sizeof(RDTStatePerCore) * cs->nr_cores); + CPU_FOREACH(cs) { + RDTStatePerCore *rdt = &rdtDev->rdtInstances[cs->cpu_index]; + X86CPU *cpu = X86_CPU(cs); + + rdt->rdtstate = rdtDev; + cpu->rdt = rdt; + + rdt->monitors = g_malloc(sizeof(RDTMonitor) * rdtDev->rmids); + rdt->rdtstate->allocations = g_malloc(sizeof(RDTAllocation) * rdtDev->rmids); + } +} + static void rdt_finalize(Object *obj) { + CPUState *cs; + RDTState *rdt = RDT(obj); + + CPU_FOREACH(cs) { + RDTStatePerCore *rdtInstance = &rdt->rdtInstances[cs->cpu_index]; + g_free(rdtInstance->monitors); + g_free(rdtInstance->rdtstate->allocations); + } + + g_free(rdt->rdtInstances); } static void rdt_class_init(ObjectClass *klass, void *data) @@ -XXX,XX +XXX,XX @@ static void rdt_class_init(ObjectClass *klass, void *data) dc->hotpluggable = false; dc->desc = "RDT"; dc->user_creatable = true; + dc->realize = rdt_realize; device_class_set_props(dc, rdt_properties); } -- 2.46.0.469.g59c65b2a67-goog From: ‪Hendrik Wüthrich <whendrik@google.com> Add RDT code to Associate CLOSID with RMID / set RMID for monitoring, write COS, and read monitoring data. This patch does not add code for the guest to interact through these things with MSRs, only the actual ability for the RDT device to do them. Signed-off-by: Hendrik Wüthrich <whendrik@google.com> --- hw/i386/rdt.c | 124 ++++++++++++++++++++++++++++++++++++++++++ include/hw/i386/rdt.h | 16 ++++++ 2 files changed, 140 insertions(+) diff --git a/hw/i386/rdt.c b/hw/i386/rdt.c index XXXXXXX..XXXXXXX 100644 --- a/hw/i386/rdt.c +++ b/hw/i386/rdt.c @@ -XXX,XX +XXX,XX @@ #include "qom/object.h" #include "target/i386/cpu.h" +/* RDT Monitoring Event Codes */ +#define RDT_EVENT_L3_OCCUPANCY 1 +#define RDT_EVENT_L3_REMOTE_BW 2 +#define RDT_EVENT_L3_LOCAL_BW 3 + /* Max counts for allocation masks or CBMs. In other words, the size of respective MSRs*/ #define RDT_MAX_L3_MASK_COUNT 128 #define RDT_MAX_L2_MASK_COUNT 48 @@ -XXX,XX +XXX,XX @@ #define TYPE_RDT "rdt" #define RDT_NUM_RMID_PROP "rmids" +#define QM_CTR_ERROR (1ULL << 63) +#define QM_CTR_UNAVAILABLE (1ULL << 62) + OBJECT_DECLARE_TYPE(RDTState, RDTStateClass, RDT); struct RDTMonitor { @@ -XXX,XX +XXX,XX @@ struct RDTState { struct RDTStateClass { }; +bool rdt_associate_rmid_cos(uint64_t msr_ia32_pqr_assoc) { + X86CPU *cpu = X86_CPU(current_cpu); + RDTStatePerCore *rdt = cpu->rdt; + RDTAllocation *alloc; + + uint32_t cos_id = (msr_ia32_pqr_assoc & 0xffff0000) >> 16; + uint32_t rmid = msr_ia32_pqr_assoc & 0xffff; + + if (cos_id > RDT_MAX_L3_MASK_COUNT || cos_id > RDT_MAX_L2_MASK_COUNT || + cos_id > RDT_MAX_MBA_THRTL_COUNT || rmid > rdt_max_rmid(rdt)) { + return false; + } + + rdt->active_rmid = rmid; + + alloc = &rdt->rdtstate->allocations[rmid]; + + alloc->active_cos = cos_id; + + return true; +} + +uint32_t rdt_read_l3_mask(uint32_t pos) +{ + X86CPU *cpu = X86_CPU(current_cpu); + RDTStatePerCore *rdt = cpu->rdt; + + uint32_t val = rdt->rdtstate->msr_L3_ia32_mask_n[pos]; + return val; +} + +uint32_t rdt_read_l2_mask(uint32_t pos) +{ + X86CPU *cpu = X86_CPU(current_cpu); + RDTStatePerCore *rdt = cpu->rdt; + + uint32_t val = rdt->rdtstate->msr_L2_ia32_mask_n[pos]; + return val; +} + +uint32_t rdt_read_mba_thrtl(uint32_t pos) +{ + X86CPU *cpu = X86_CPU(current_cpu); + RDTStatePerCore *rdt = cpu->rdt; + + uint32_t val = rdt->rdtstate->ia32_L2_qos_ext_bw_thrtl_n[pos]; + return val; +} + +void rdt_write_msr_l3_mask(uint32_t pos, uint32_t val) { + X86CPU *cpu = X86_CPU(current_cpu); + RDTStatePerCore *rdt = cpu->rdt; + + rdt->rdtstate->msr_L3_ia32_mask_n[pos] = val; +} + +void rdt_write_msr_l2_mask(uint32_t pos, uint32_t val) { + X86CPU *cpu = X86_CPU(current_cpu); + RDTStatePerCore *rdt = cpu->rdt; + + rdt->rdtstate->msr_L2_ia32_mask_n[pos] = val; +} + +void rdt_write_mba_thrtl(uint32_t pos, uint32_t val) { + X86CPU *cpu = X86_CPU(current_cpu); + RDTStatePerCore *rdt = cpu->rdt; + + rdt->rdtstate->ia32_L2_qos_ext_bw_thrtl_n[pos] = val; +} + +uint32_t rdt_max_rmid(RDTStatePerCore *rdt) +{ + RDTState *rdtdev = rdt->rdtstate; + return rdtdev->rmids - 1; +} + +uint64_t rdt_read_event_count(RDTStatePerCore *rdtInstance, uint32_t rmid, uint32_t event_id) +{ + CPUState *cs; + RDTMonitor *mon; + RDTState *rdt = rdtInstance->rdtstate; + + uint32_t count_l3 = 0; + uint32_t count_local = 0; + uint32_t count_remote = 0; + + if (!rdt) { + return 0; + } + + CPU_FOREACH(cs) { + rdtInstance = &rdt->rdtInstances[cs->cpu_index]; + if (rmid >= rdtInstance->monitors->len) { + return QM_CTR_ERROR; + } + mon = &g_array_index(rdtInstance->monitors, RDTMonitor, rmid); + count_l3 += mon->count_l3; + count_local += mon->count_local; + count_remote += mon->count_remote; + } + + switch (event_id) { + case RDT_EVENT_L3_OCCUPANCY: + return count_l3 == 0 ? QM_CTR_UNAVAILABLE : count_l3; + break; + case RDT_EVENT_L3_REMOTE_BW: + return count_remote == 0 ? QM_CTR_UNAVAILABLE : count_remote; + break; + case RDT_EVENT_L3_LOCAL_BW: + return count_local == 0 ? QM_CTR_UNAVAILABLE : count_local; + break; + default: + return QM_CTR_ERROR; + } +} + OBJECT_DEFINE_TYPE(RDTState, rdt, RDT, ISA_DEVICE); static Property rdt_properties[] = { diff --git a/include/hw/i386/rdt.h b/include/hw/i386/rdt.h index XXXXXXX..XXXXXXX 100644 --- a/include/hw/i386/rdt.h +++ b/include/hw/i386/rdt.h @@ -XXX,XX +XXX,XX @@ #ifndef HW_RDT_H #define HW_RDT_H +#include <stdbool.h> +#include <stdint.h> + typedef struct RDTState RDTState; typedef struct RDTStatePerCore RDTStatePerCore; typedef struct RDTMonitor RDTMonitor; typedef struct RDTAllocation RDTAllocation; +bool rdt_associate_rmid_cos(uint64_t msr_ia32_pqr_assoc); + +void rdt_write_msr_l3_mask(uint32_t pos, uint32_t val); +void rdt_write_msr_l2_mask(uint32_t pos, uint32_t val); +void rdt_write_mba_thrtl(uint32_t pos, uint32_t val); + +uint32_t rdt_read_l3_mask(uint32_t pos); +uint32_t rdt_read_l2_mask(uint32_t pos); +uint32_t rdt_read_mba_thrtl(uint32_t pos); + +uint64_t rdt_read_event_count(RDTStatePerCore *rdt, uint32_t rmid, uint32_t event_id); +uint32_t rdt_max_rmid(RDTStatePerCore *rdt); + #endif -- 2.46.0.469.g59c65b2a67-goog From: ‪Hendrik Wüthrich <whendrik@google.com> Implement rdmsr and wrmsr for the following MSRs: * MSR_IA32_PQR_ASSOC * MSR_IA32_QM_EVTSEL * MSR_IA32_QM_CTR * IA32_L3_QOS_Mask_n * IA32_L2_QOS_Mask_n * IA32_L2_QoS_Ext_BW_Thrtl_n This allows for the guest to call RDT-internal functions to associate an RMID with a CLOSID / set an active RMID for monitoring, read monitoring data, and set classes of service. Signed-off-by: Hendrik Wüthrich <whendrik@google.com> --- hw/i386/rdt.c | 22 ++++---- include/hw/i386/rdt.h | 4 ++ target/i386/cpu.h | 14 +++++ target/i386/tcg/sysemu/misc_helper.c | 84 ++++++++++++++++++++++++++++ 4 files changed, 112 insertions(+), 12 deletions(-) diff --git a/hw/i386/rdt.c b/hw/i386/rdt.c index XXXXXXX..XXXXXXX 100644 --- a/hw/i386/rdt.c +++ b/hw/i386/rdt.c @@ -XXX,XX +XXX,XX @@ struct RDTState { struct RDTStateClass { }; +uint32_t rdt_get_cpuid_10_1_edx_cos_max(void) { return RDT_MAX_L3_MASK_COUNT; } +uint32_t rdt_get_cpuid_10_2_edx_cos_max(void) { return RDT_MAX_L2_MASK_COUNT; } +uint32_t rdt_get_cpuid_10_3_edx_cos_max(void) { return RDT_MAX_MBA_THRTL_COUNT; } + bool rdt_associate_rmid_cos(uint64_t msr_ia32_pqr_assoc) { X86CPU *cpu = X86_CPU(current_cpu); RDTStatePerCore *rdt = cpu->rdt; @@ -XXX,XX +XXX,XX @@ bool rdt_associate_rmid_cos(uint64_t msr_ia32_pqr_assoc) { uint32_t rmid = msr_ia32_pqr_assoc & 0xffff; if (cos_id > RDT_MAX_L3_MASK_COUNT || cos_id > RDT_MAX_L2_MASK_COUNT || - cos_id > RDT_MAX_MBA_THRTL_COUNT || rmid > rdt_max_rmid(rdt)) { + cos_id > RDT_MAX_MBA_THRTL_COUNT || rmid > rdt_max_rmid(rdt)) { return false; } @@ -XXX,XX +XXX,XX @@ uint32_t rdt_read_l3_mask(uint32_t pos) X86CPU *cpu = X86_CPU(current_cpu); RDTStatePerCore *rdt = cpu->rdt; - uint32_t val = rdt->rdtstate->msr_L3_ia32_mask_n[pos]; - return val; + return rdt->rdtstate->msr_L3_ia32_mask_n[pos]; } uint32_t rdt_read_l2_mask(uint32_t pos) @@ -XXX,XX +XXX,XX @@ uint32_t rdt_read_l2_mask(uint32_t pos) X86CPU *cpu = X86_CPU(current_cpu); RDTStatePerCore *rdt = cpu->rdt; - uint32_t val = rdt->rdtstate->msr_L2_ia32_mask_n[pos]; - return val; + return rdt->rdtstate->msr_L2_ia32_mask_n[pos]; } uint32_t rdt_read_mba_thrtl(uint32_t pos) @@ -XXX,XX +XXX,XX @@ uint32_t rdt_read_mba_thrtl(uint32_t pos) X86CPU *cpu = X86_CPU(current_cpu); RDTStatePerCore *rdt = cpu->rdt; - uint32_t val = rdt->rdtstate->ia32_L2_qos_ext_bw_thrtl_n[pos]; - return val; + return rdt->rdtstate->ia32_L2_qos_ext_bw_thrtl_n[pos]; } void rdt_write_msr_l3_mask(uint32_t pos, uint32_t val) { @@ -XXX,XX +XXX,XX @@ uint32_t rdt_max_rmid(RDTStatePerCore *rdt) return rdtdev->rmids - 1; } -uint64_t rdt_read_event_count(RDTStatePerCore *rdtInstance, uint32_t rmid, uint32_t event_id) +uint64_t rdt_read_event_count(RDTStatePerCore *rdtInstance, + uint32_t rmid, uint32_t event_id) { CPUState *cs; RDTMonitor *mon; @@ -XXX,XX +XXX,XX @@ uint64_t rdt_read_event_count(RDTStatePerCore *rdtInstance, uint32_t rmid, uint3 switch (event_id) { case RDT_EVENT_L3_OCCUPANCY: return count_l3 == 0 ? QM_CTR_UNAVAILABLE : count_l3; - break; case RDT_EVENT_L3_REMOTE_BW: return count_remote == 0 ? QM_CTR_UNAVAILABLE : count_remote; - break; case RDT_EVENT_L3_LOCAL_BW: return count_local == 0 ? QM_CTR_UNAVAILABLE : count_local; - break; default: return QM_CTR_ERROR; } @@ -XXX,XX +XXX,XX @@ static void rdt_class_init(ObjectClass *klass, void *data) device_class_set_props(dc, rdt_properties); } - diff --git a/include/hw/i386/rdt.h b/include/hw/i386/rdt.h index XXXXXXX..XXXXXXX 100644 --- a/include/hw/i386/rdt.h +++ b/include/hw/i386/rdt.h @@ -XXX,XX +XXX,XX @@ typedef struct RDTStatePerCore RDTStatePerCore; typedef struct RDTMonitor RDTMonitor; typedef struct RDTAllocation RDTAllocation; +uint32_t rdt_get_cpuid_10_1_edx_cos_max(void); +uint32_t rdt_get_cpuid_10_2_edx_cos_max(void); +uint32_t rdt_get_cpuid_10_3_edx_cos_max(void); + bool rdt_associate_rmid_cos(uint64_t msr_ia32_pqr_assoc); void rdt_write_msr_l3_mask(uint32_t pos, uint32_t val); diff --git a/target/i386/cpu.h b/target/i386/cpu.h index XXXXXXX..XXXXXXX 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -XXX,XX +XXX,XX @@ typedef enum X86Seg { #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490 #define MSR_IA32_VMX_VMFUNC 0x00000491 +#define MSR_IA32_QM_EVTSEL 0x0c8d +#define MSR_IA32_QM_CTR 0x0c8e +#define MSR_IA32_PQR_ASSOC 0x0c8f + +#define MSR_IA32_L3_CBM_BASE 0x0c90 +#define MSR_IA32_L3_MASKS_END 0x0d0f +#define MSR_IA32_L2_CBM_BASE 0x0d10 +#define MSR_IA32_L2_CBM_END 0x0d4f +#define MSR_IA32_L2_QOS_Ext_BW_Thrtl_BASE 0xd50 +#define MSR_IA32_L2_QOS_Ext_BW_Thrtl_END 0xd80 + #define MSR_APIC_START 0x00000800 #define MSR_APIC_END 0x000008ff @@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState { uint64_t msr_ia32_feature_control; uint64_t msr_ia32_sgxlepubkeyhash[4]; + uint64_t msr_ia32_qm_evtsel; + uint64_t msr_ia32_pqr_assoc; + uint64_t msr_fixed_ctr_ctrl; uint64_t msr_global_ctrl; uint64_t msr_global_status; diff --git a/target/i386/tcg/sysemu/misc_helper.c b/target/i386/tcg/sysemu/misc_helper.c index XXXXXXX..XXXXXXX 100644 --- a/target/i386/tcg/sysemu/misc_helper.c +++ b/target/i386/tcg/sysemu/misc_helper.c @@ -XXX,XX +XXX,XX @@ #include "exec/address-spaces.h" #include "exec/exec-all.h" #include "tcg/helper-tcg.h" +#include "hw/i386/rdt.h" #include "hw/i386/apic.h" void helper_outb(CPUX86State *env, uint32_t port, uint32_t data) @@ -XXX,XX +XXX,XX @@ void helper_wrmsr(CPUX86State *env) env->msr_bndcfgs = val; cpu_sync_bndcs_hflags(env); break; + case MSR_IA32_QM_EVTSEL: + env->msr_ia32_qm_evtsel = val; + break; + case MSR_IA32_PQR_ASSOC: + { + env->msr_ia32_pqr_assoc = val; + + if (!rdt_associate_rmid_cos(val)) + goto error; + break; + } + case MSR_IA32_L3_CBM_BASE ... MSR_IA32_L3_MASKS_END: + { + uint32_t pos = (uint32_t)env->regs[R_ECX] - MSR_IA32_L3_CBM_BASE; + + if (pos >= rdt_get_cpuid_10_1_edx_cos_max()) { + goto error; + } + rdt_write_msr_l3_mask(pos, val); + break; + } + case MSR_IA32_L2_CBM_BASE ... MSR_IA32_L2_CBM_END: + { + uint32_t pos = (uint32_t)env->regs[R_ECX] - MSR_IA32_L2_CBM_BASE; + + if (pos >= rdt_get_cpuid_10_2_edx_cos_max()) { + goto error; + } + rdt_write_msr_l2_mask(pos, val); + break; + } + case MSR_IA32_L2_QOS_Ext_BW_Thrtl_BASE ... MSR_IA32_L2_QOS_Ext_BW_Thrtl_END: + { + uint32_t pos = (uint32_t)env->regs[R_ECX] - MSR_IA32_L2_QOS_Ext_BW_Thrtl_BASE; + + if (pos >= rdt_get_cpuid_10_3_edx_cos_max()) { + goto error; + } + rdt_write_mba_thrtl(pos, val); + break; + } case MSR_APIC_START ... MSR_APIC_END: { int ret; int index = (uint32_t)env->regs[R_ECX] - MSR_APIC_START; @@ -XXX,XX +XXX,XX @@ void helper_rdmsr(CPUX86State *env) val = (cs->nr_threads * cs->nr_cores) | (cs->nr_cores << 16); break; } + case MSR_IA32_QM_CTR: + val = rdt_read_event_count(x86_cpu->rdt, + (env->msr_ia32_qm_evtsel >> 32) & 0xff, + env->msr_ia32_qm_evtsel & 0xff); + break; + case MSR_IA32_QM_EVTSEL: + val = env->msr_ia32_qm_evtsel; + break; + case MSR_IA32_PQR_ASSOC: + val = env->msr_ia32_pqr_assoc; + break; + case MSR_IA32_L3_CBM_BASE ... MSR_IA32_L3_MASKS_END: + { + uint32_t pos = (uint32_t)env->regs[R_ECX] - MSR_IA32_L3_CBM_BASE; + + if (pos >= rdt_get_cpuid_10_1_edx_cos_max()) { + raise_exception_err_ra(env, EXCP0D_GPF, 0, GETPC()); + } + val = rdt_read_l3_mask(pos); + break; + } + case MSR_IA32_L2_CBM_BASE ... MSR_IA32_L2_CBM_END: + { + uint32_t pos = (uint32_t)env->regs[R_ECX] - MSR_IA32_L2_CBM_BASE; + + if (pos >= rdt_get_cpuid_10_2_edx_cos_max()) { + raise_exception_err_ra(env, EXCP0D_GPF, 0, GETPC()); + } + val = rdt_read_l2_mask(pos); + break; + } + case MSR_IA32_L2_QOS_Ext_BW_Thrtl_BASE ... MSR_IA32_L2_QOS_Ext_BW_Thrtl_END: + { + uint32_t pos = (uint32_t)env->regs[R_ECX] - MSR_IA32_L2_QOS_Ext_BW_Thrtl_BASE; + + if (pos >= rdt_get_cpuid_10_3_edx_cos_max()) { + raise_exception_err_ra(env, EXCP0D_GPF, 0, GETPC()); + } + val = rdt_read_mba_thrtl(pos); + break; + } case MSR_APIC_START ... MSR_APIC_END: { int ret; int index = (uint32_t)env->regs[R_ECX] - MSR_APIC_START; @@ -XXX,XX +XXX,XX @@ void helper_rdmsr(CPUX86State *env) } env->regs[R_EAX] = (uint32_t)(val); env->regs[R_EDX] = (uint32_t)(val >> 32); + return; } void helper_flush_page(CPUX86State *env, target_ulong addr) -- 2.46.0.469.g59c65b2a67-goog From: ‪Hendrik Wüthrich <whendrik@google.com> Add CPUID enumeration for intel RDT monitoring and allocation, as well as the flags used in the enumeration code. Signed-off-by: Hendrik Wüthrich <whendrik@google.com> --- hw/i386/rdt.c | 33 +++++++++++++++++++++++ include/hw/i386/rdt.h | 31 +++++++++++++++++++++ target/i386/cpu.c | 63 +++++++++++++++++++++++++++++++++++++++++++ target/i386/cpu.h | 5 ++++ 4 files changed, 132 insertions(+) diff --git a/hw/i386/rdt.c b/hw/i386/rdt.c index XXXXXXX..XXXXXXX 100644 --- a/hw/i386/rdt.c +++ b/hw/i386/rdt.c @@ -XXX,XX +XXX,XX @@ #define RDT_MAX_L2_MASK_COUNT 48 #define RDT_MAX_MBA_THRTL_COUNT 31 +/* RDT L3 Allocation features */ +#define CPUID_10_1_EAX_CBM_LENGTH 0xf +#define CPUID_10_1_EBX_CBM 0x0 +#define CPUID_10_1_ECX_CDP 0x0 // to enable, it would be (1U << 2) +#define CPUID_10_1_EDX_COS_MAX MAX_L3_MASK_COUNT +/* RDT L2 Allocation features*/ +#define CPUID_10_2_EAX_CBM_LENGTH 0xf +#define CPUID_10_2_EBX_CBM 0x0 +#define CPUID_10_2_EDX_COS_MAX MAX_L2_MASK_COUNT +/* RDT MBA features */ +#define CPUID_10_3_EAX_THRTL_MAX 89 +#define CPUID_10_3_ECX_LINEAR_RESPONSE (1U << 2) +#define CPUID_10_3_EDX_COS_MAX MAX_MBA_THRTL_COUNT + #define TYPE_RDT "rdt" #define RDT_NUM_RMID_PROP "rmids" @@ -XXX,XX +XXX,XX @@ struct RDTState { struct RDTStateClass { }; +uint32_t rdt_get_cpuid_15_0_edx_l3(void) { return CPUID_15_1_EDX_L3_OCCUPANCY | CPUID_15_1_EDX_L3_TOTAL_BW | CPUID_15_1_EDX_L3_LOCAL_BW; } + +uint32_t rdt_cpuid_15_1_edx_l3_total_bw_enabled(void) { return CPUID_15_1_EDX_L3_TOTAL_BW; } +uint32_t rdt_cpuid_15_1_edx_l3_local_bw_enabled(void) { return CPUID_15_1_EDX_L3_LOCAL_BW; } +uint32_t rdt_cpuid_15_1_edx_l3_occupancy_enabled(void) { return CPUID_15_1_EDX_L3_OCCUPANCY; } + +uint32_t rdt_cpuid_10_0_ebx_l3_cat_enabled(void) { return CPUID_10_0_EBX_L3_CAT; } +uint32_t rdt_cpuid_10_0_ebx_l2_cat_enabled(void) { return CPUID_10_0_EBX_L2_CAT; } +uint32_t rdt_cpuid_10_0_ebx_l2_mba_enabled(void) { return CPUID_10_0_EBX_MBA; } + +uint32_t rdt_get_cpuid_10_1_eax_cbm_length(void) { return CPUID_10_1_EAX_CBM_LENGTH; } +uint32_t rdt_cpuid_10_1_ebx_cbm_enabled(void) { return CPUID_10_1_EBX_CBM; } +uint32_t rdt_cpuid_10_1_ecx_cdp_enabled(void) { return CPUID_10_1_ECX_CDP; } uint32_t rdt_get_cpuid_10_1_edx_cos_max(void) { return RDT_MAX_L3_MASK_COUNT; } + +uint32_t rdt_get_cpuid_10_2_eax_cbm_length(void) { return CPUID_10_2_EAX_CBM_LENGTH; } +uint32_t rdt_cpuid_10_2_ebx_cbm_enabled(void) { return CPUID_10_2_EBX_CBM; } uint32_t rdt_get_cpuid_10_2_edx_cos_max(void) { return RDT_MAX_L2_MASK_COUNT; } + +uint32_t rdt_get_cpuid_10_3_eax_thrtl_max(void) { return CPUID_10_3_EAX_THRTL_MAX; } +uint32_t rdt_cpuid_10_3_eax_linear_response_enabled(void) { return CPUID_10_3_ECX_LINEAR_RESPONSE; } uint32_t rdt_get_cpuid_10_3_edx_cos_max(void) { return RDT_MAX_MBA_THRTL_COUNT; } bool rdt_associate_rmid_cos(uint64_t msr_ia32_pqr_assoc) { diff --git a/include/hw/i386/rdt.h b/include/hw/i386/rdt.h index XXXXXXX..XXXXXXX 100644 --- a/include/hw/i386/rdt.h +++ b/include/hw/i386/rdt.h @@ -XXX,XX +XXX,XX @@ #include <stdbool.h> #include <stdint.h> +/* RDT L3 Cache Monitoring Technology */ +#define CPUID_15_0_EDX_L3 (1U << 1) +#define CPUID_15_1_EDX_L3_OCCUPANCY (1U << 0) +#define CPUID_15_1_EDX_L3_TOTAL_BW (1U << 1) +#define CPUID_15_1_EDX_L3_LOCAL_BW (1U << 2) + +/* RDT Cache Allocation Technology */ +#define CPUID_10_0_EBX_L3_CAT (1U << 1) +#define CPUID_10_0_EBX_L2_CAT (1U << 2) +#define CPUID_10_0_EBX_MBA (1U << 3) +#define CPUID_10_0_EDX CPUID_10_0_EBX_L3_CAT | CPUID_10_0_EBX_L2_CAT | CPUID_10_0_EBX_MBA + typedef struct RDTState RDTState; typedef struct RDTStatePerCore RDTStatePerCore; typedef struct RDTMonitor RDTMonitor; typedef struct RDTAllocation RDTAllocation; +uint32_t rdt_get_cpuid_15_0_edx_l3(void); + +uint32_t rdt_cpuid_15_1_edx_l3_total_bw_enabled(void); +uint32_t rdt_cpuid_15_1_edx_l3_local_bw_enabled(void); +uint32_t rdt_cpuid_15_1_edx_l3_occupancy_enabled(void); + +uint32_t rdt_cpuid_10_0_ebx_l3_cat_enabled(void); +uint32_t rdt_cpuid_10_0_ebx_l2_cat_enabled(void); +uint32_t rdt_cpuid_10_0_ebx_l2_mba_enabled(void); + +uint32_t rdt_get_cpuid_10_1_eax_cbm_length(void); +uint32_t rdt_cpuid_10_1_ebx_cbm_enabled(void); +uint32_t rdt_cpuid_10_1_ecx_cdp_enabled(void); uint32_t rdt_get_cpuid_10_1_edx_cos_max(void); + +uint32_t rdt_get_cpuid_10_2_eax_cbm_length(void); +uint32_t rdt_cpuid_10_2_ebx_cbm_enabled(void); uint32_t rdt_get_cpuid_10_2_edx_cos_max(void); + +uint32_t rdt_get_cpuid_10_3_eax_thrtl_max(void); +uint32_t rdt_cpuid_10_3_eax_linear_response_enabled(void); uint32_t rdt_get_cpuid_10_3_edx_cos_max(void); bool rdt_associate_rmid_cos(uint64_t msr_ia32_pqr_assoc); diff --git a/target/i386/cpu.c b/target/i386/cpu.c index XXXXXXX..XXXXXXX 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -XXX,XX +XXX,XX @@ #include "hw/boards.h" #include "hw/i386/sgx-epc.h" #endif +#include "hw/i386/rdt.h" #include "disas/capstone.h" #include "cpu-internal.h" @@ -XXX,XX +XXX,XX @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, assert(!(*eax & ~0x1f)); *ebx &= 0xffff; /* The count doesn't need to be reliable. */ break; +#ifndef CONFIG_USER_ONLY + case 0xF: + /* Shared Resource Monitoring Enumeration Leaf */ + *eax = 0; + *ebx = 0; + *ecx = 0; + *edx = 0; + if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_PQM)) + break; + assert(cpu->rdt); + /* Non-zero count is ResId */ + switch (count) { + /* Monitoring Resource Type Enumeration */ + case 0: + *edx = env->features[FEAT_RDT_15_0_EDX]; + *ebx = rdt_max_rmid(cpu->rdt); + break; + case 1: + *ebx = 1; + *ecx = rdt_max_rmid(cpu->rdt); + *edx = rdt_cpuid_15_1_edx_l3_total_bw_enabled() | + rdt_cpuid_15_1_edx_l3_local_bw_enabled() | + rdt_cpuid_15_1_edx_l3_occupancy_enabled(); + break; + } + break; + case 0x10: + /* Shared Resource Director Technology Allocation Enumeration Leaf */ + *eax = 0; + *ebx = 0; + *ecx = 0; + *edx = 0; + if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_PQE)) + break; + assert(cpu->rdt); + /* Non-zero count is ResId */ + switch (count) { + /* Cache Allocation Technology Available Resource Types */ + case 0: + *ebx |= rdt_cpuid_10_0_ebx_l3_cat_enabled(); + *ebx |= rdt_cpuid_10_0_ebx_l2_cat_enabled(); + *ebx |= rdt_cpuid_10_0_ebx_l2_mba_enabled(); + break; + case 1: + *eax = rdt_get_cpuid_10_1_eax_cbm_length(); + *ebx = rdt_cpuid_10_1_ebx_cbm_enabled(); + *ecx |= rdt_cpuid_10_1_ecx_cdp_enabled(); + *edx = rdt_get_cpuid_10_1_edx_cos_max(); + break; + case 2: + *eax = rdt_get_cpuid_10_2_eax_cbm_length(); + *ebx = rdt_cpuid_10_2_ebx_cbm_enabled(); + *edx = rdt_get_cpuid_10_2_edx_cos_max(); + break; + case 3: + *eax = rdt_get_cpuid_10_3_eax_thrtl_max(); + *ecx = rdt_cpuid_10_3_eax_linear_response_enabled(); + *edx = rdt_get_cpuid_10_3_edx_cos_max(); + break; + } + break; +#endif case 0x1C: if (cpu->enable_pmu && (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR)) { x86_cpu_get_supported_cpuid(0x1C, 0, eax, ebx, ecx, edx); diff --git a/target/i386/cpu.h b/target/i386/cpu.h index XXXXXXX..XXXXXXX 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -XXX,XX +XXX,XX @@ typedef enum FeatureWord { FEAT_XSAVE_XSS_HI, /* CPUID[EAX=0xd,ECX=1].EDX */ FEAT_7_1_EDX, /* CPUID[EAX=7,ECX=1].EDX */ FEAT_7_2_EDX, /* CPUID[EAX=7,ECX=2].EDX */ + FEAT_RDT_15_0_EDX, /* CPUID[EAX=0xf,ECX=0].EDX (RDT CMT/MBM) */ FEATURE_WORDS, } FeatureWord; @@ -XXX,XX +XXX,XX @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU *cpu, FeatureWord w); #define CPUID_7_0_EBX_INVPCID (1U << 10) /* Restricted Transactional Memory */ #define CPUID_7_0_EBX_RTM (1U << 11) +/* Resource Director Technology Monitoring */ +#define CPUID_7_0_EBX_PQM (1U << 12) /* Memory Protection Extension */ #define CPUID_7_0_EBX_MPX (1U << 14) +/* Resource Director Technology Allocation */ +#define CPUID_7_0_EBX_PQE (1U << 15) /* AVX-512 Foundation */ #define CPUID_7_0_EBX_AVX512F (1U << 16) /* AVX-512 Doubleword & Quadword Instruction */ -- 2.46.0.469.g59c65b2a67-goog From: ‪Hendrik Wüthrich <whendrik@google.com> Add RDT features to feature word / TCG. Signed-off-by: Hendrik Wüthrich <whendrik@google.com> --- target/i386/cpu.c | 30 ++++++++++++++++++++++++++++-- target/i386/cpu.h | 2 ++ 2 files changed, 30 insertions(+), 2 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index XXXXXXX..XXXXXXX 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -XXX,XX +XXX,XX @@ void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1, CPUID_7_0_EBX_CLFLUSHOPT | \ CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \ CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_RDSEED | \ - CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_KERNEL_FEATURES) + CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_KERNEL_FEATURES | \ + CPUID_7_0_EBX_PQM | CPUID_7_0_EBX_PQE) /* missing: CPUID_7_0_EBX_HLE CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM */ @@ -XXX,XX +XXX,XX @@ void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1, #define TCG_SGX_12_0_EAX_FEATURES 0 #define TCG_SGX_12_0_EBX_FEATURES 0 #define TCG_SGX_12_1_EAX_FEATURES 0 +#define TCG_RDT_15_0_EDX_FEATURES CPUID_15_0_EDX_L3 #if defined CONFIG_USER_ONLY #define CPUID_8000_0008_EBX_KERNEL_FEATURES (CPUID_8000_0008_EBX_IBPB | \ @@ -XXX,XX +XXX,XX @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = { "fsgsbase", "tsc-adjust", "sgx", "bmi1", "hle", "avx2", NULL, "smep", "bmi2", "erms", "invpcid", "rtm", - NULL, NULL, "mpx", NULL, + "rdt-m", NULL, "mpx", "rdt-a", "avx512f", "avx512dq", "rdseed", "adx", "smap", "avx512ifma", "pcommit", "clflushopt", "clwb", "intel-pt", "avx512pf", "avx512er", @@ -XXX,XX +XXX,XX @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = { }, .tcg_features = TCG_SGX_12_1_EAX_FEATURES, }, + + [FEAT_RDT_10_0_EBX] = { + .type = CPUID_FEATURE_WORD, + .feat_names = { + NULL, "l3-cat", "l2-cat", "mba" + }, + .cpuid = { + .eax = 0x10, + .needs_ecx = true, .ecx = 0, + .reg = R_EBX, + } + }, + [FEAT_RDT_15_0_EDX] = { + .type = CPUID_FEATURE_WORD, + .feat_names = { + [1] = "l3-cmt" + }, + .cpuid = { + .eax = 0xf, + .needs_ecx = true, .ecx = 0, + .reg = R_EDX, + }, + .tcg_features = TCG_RDT_15_0_EDX_FEATURES, + }, }; typedef struct FeatureMask { diff --git a/target/i386/cpu.h b/target/i386/cpu.h index XXXXXXX..XXXXXXX 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -XXX,XX +XXX,XX @@ typedef enum FeatureWord { FEAT_XSAVE_XSS_HI, /* CPUID[EAX=0xd,ECX=1].EDX */ FEAT_7_1_EDX, /* CPUID[EAX=7,ECX=1].EDX */ FEAT_7_2_EDX, /* CPUID[EAX=7,ECX=2].EDX */ + FEAT_RDT_15_0_EBX, /* CPUID[EAX=0xf,ECX=0].EBX (RDT CMT/MBM) */ FEAT_RDT_15_0_EDX, /* CPUID[EAX=0xf,ECX=0].EDX (RDT CMT/MBM) */ + FEAT_RDT_10_0_EBX, /* CPUID[EAX=0x10,ECX=0].EBX (RDT CAT/MBA) */ FEATURE_WORDS, } FeatureWord; -- 2.46.0.469.g59c65b2a67-goog From: ‪Hendrik Wüthrich <whendrik@google.com> Adjust minimum CPUID level if RDT monitoring or allocation features are enabled to ensure that CPUID will return them. Signed-off-by: Hendrik Wüthrich <whendrik@google.com> --- target/i386/cpu.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index XXXXXXX..XXXXXXX 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -XXX,XX +XXX,XX @@ void x86_cpu_expand_features(X86CPU *cpu, Error **errp) if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SGX) { x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x12); } + + /* RDT monitoring requires CPUID[0xF] */ + if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_PQM) { + x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0xF); + } + + /* RDT allocation requires CPUID[0x10] */ + if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_PQE) { + x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x10); + } } /* Set cpuid_*level* based on cpuid_min_*level, if not explicitly set */ -- 2.46.0.469.g59c65b2a67-goog From: ‪Hendrik Wüthrich <whendrik@google.com> Make sure that RDT monitoring and allocation features are included in in full_cpuid_auto_level. Signed-off-by: Hendrik Wüthrich <whendrik@google.com> --- target/i386/cpu.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index XXXXXXX..XXXXXXX 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -XXX,XX +XXX,XX @@ void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1, #else #define TCG_7_0_ECX_RDPID 0 #endif + #define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | \ /* CPUID_7_0_ECX_OSPKE is dynamic */ \ CPUID_7_0_ECX_LA57 | CPUID_7_0_ECX_PKS | CPUID_7_0_ECX_VAES | \ @@ -XXX,XX +XXX,XX @@ void x86_cpu_expand_features(X86CPU *cpu, Error **errp) x86_cpu_adjust_feat_level(cpu, FEAT_C000_0001_EDX); x86_cpu_adjust_feat_level(cpu, FEAT_SVM); x86_cpu_adjust_feat_level(cpu, FEAT_XSAVE); + x86_cpu_adjust_feat_level(cpu, FEAT_RDT_15_0_EDX); + x86_cpu_adjust_feat_level(cpu, FEAT_RDT_10_0_EBX); /* Intel Processor Trace requires CPUID[0x14] */ if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT)) { -- 2.46.0.469.g59c65b2a67-goog