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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-427d2a8e420sm14059315e9.35.2024.07.18.06.20.38 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Jul 2024 06:20:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1721308839; x=1721913639; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=4YsbRAcT7lsG9lpifKyGsg4DpvurXs++XIcvW/WT4VE=; b=e7kniiFF0YxsDIRtdbc5fI58HmBgQe1uHLjWHj9xUg7D/HTVXQkHfikP/IVClxaGnh 2o96e1lVujRvKBmP9RlO5N2DGo/uyBkrZb6o5V08LRH6wup93+CA/xL+v/g+moF7j73E bWq7mCe9I/bWwPUwDpUeSPLvR4h068125X6HA1E+Z3nsciWfk3FKjTrM/k4jJ48vLB0p SU9PjWmvTKYIU+FsgcJOfEjRKeb22p5a/hI0znPaaJTxV/10xBh2HZCNAXemIqOdqHJq WtxdL3zNLLpOeZ7gWX3RYmTMxwDLlVBYYykk7aIeteNwbLbLr5aPR3uf5vxdPthkDat2 tMeQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1721308839; x=1721913639; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4YsbRAcT7lsG9lpifKyGsg4DpvurXs++XIcvW/WT4VE=; b=j06HytmQ3sR2a1QjnnbQBCieSYeZqFVdtdLLxMAM0snQxxTXDYpc5DbwvbT4NqIGq+ BnNdOZYanOGjv32lf/VyVNwl9MltJR+NAmZOCl0HYhvIbKThXCUI4qMpX2kWrBP/hiVE pKdhErdAVzZgfw5YMErwutNjEl3XJZA5KNCUCI1dUQFL31iKiVT7p92w74VUIOZki3N4 7p52LcDmf3nlI+axMq+14jfV2U4EQsJ9YcucUV2eFZY3BO1FOdg0k/K2qgHKon8lNQnO 3ALvYF2Im7NZXE4g5U66XoLokzwUe0n672NxEx/I732CL1CaMz9xeiV5Qv7G1utyGhnR DPRg== X-Gm-Message-State: AOJu0Yz1PSV3KRZzW+LAUCnJG35eoXvsG+xR4ujkKbYzlsJibfEhkHeg kYQN/8DAjs+99APnoMtC5BnTlObC2zfk6wQREZEjtUuQhxOSx5hwPF/xuG4RJuKJPfJIyO3XZxv P X-Google-Smtp-Source: AGHT+IELByD129jrn92+nEn/guWZSL3W7OQj9S94rUKJUXUeSDMjQN1u4yns51cYXRWvmQ8BRbYIHw== X-Received: by 2002:a05:600c:4e88:b0:424:8be4:f2c with SMTP id 5b1f17b1804b1-427d2b35b6amr6643885e9.2.1721308839117; Thu, 18 Jul 2024 06:20:39 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 18/26] hw/arm/smmuv3: Support nested SMMUs in smmuv3_notify_iova() Date: Thu, 18 Jul 2024 14:20:20 +0100 Message-Id: <20240718132028.697927-19-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240718132028.697927-1-peter.maydell@linaro.org> References: <20240718132028.697927-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1721309057157116600 From: Mostafa Saleh IOMMUTLBEvent only understands IOVA, for stage-1 or stage-2 SMMU instances we consider the input address as the IOVA, but when nesting is used, we can't mix stage-1 and stage-2 addresses, so for nesting only stage-1 is considered the IOVA and would be notified. Signed-off-by: Mostafa Saleh Reviewed-by: Jean-Philippe Brucker Reviewed-by: Eric Auger Reviewed-by: Alex Benn=C3=A9e Message-id: 20240715084519.1189624-16-smostafa@google.com Signed-off-by: Peter Maydell --- hw/arm/smmuv3.c | 39 +++++++++++++++++++++++++-------------- hw/arm/trace-events | 2 +- 2 files changed, 26 insertions(+), 15 deletions(-) diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index b05f2ab929b..a3cb30501e6 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -1096,27 +1096,38 @@ epilogue: * @iova: iova * @tg: translation granule (if communicated through range invalidation) * @num_pages: number of @granule sized pages (if tg !=3D 0), otherwise 1 + * @stage: Which stage(1 or 2) is used */ static void smmuv3_notify_iova(IOMMUMemoryRegion *mr, IOMMUNotifier *n, int asid, int vmid, dma_addr_t iova, uint8_t tg, - uint64_t num_pages) + uint64_t num_pages, int stage) { SMMUDevice *sdev =3D container_of(mr, SMMUDevice, iommu); + SMMUEventInfo eventinfo =3D {.inval_ste_allowed =3D true}; + SMMUTransCfg *cfg =3D smmuv3_get_config(sdev, &eventinfo); IOMMUTLBEvent event; uint8_t granule; - SMMUv3State *s =3D sdev->smmu; + + if (!cfg) { + return; + } + + /* + * stage is passed from TLB invalidation commands which can be either + * stage-1 or stage-2. + * However, IOMMUTLBEvent only understands IOVA, for stage-1 or stage-2 + * SMMU instances we consider the input address as the IOVA, but when + * nesting is used, we can't mix stage-1 and stage-2 addresses, so for + * nesting only stage-1 is considered the IOVA and would be notified. + */ + if ((stage =3D=3D SMMU_STAGE_2) && (cfg->stage =3D=3D SMMU_NESTED)) + return; =20 if (!tg) { - SMMUEventInfo eventinfo =3D {.inval_ste_allowed =3D true}; - SMMUTransCfg *cfg =3D smmuv3_get_config(sdev, &eventinfo); SMMUTransTableInfo *tt; =20 - if (!cfg) { - return; - } - if (asid >=3D 0 && cfg->asid !=3D asid) { return; } @@ -1125,7 +1136,7 @@ static void smmuv3_notify_iova(IOMMUMemoryRegion *mr, return; } =20 - if (STAGE1_SUPPORTED(s)) { + if (stage =3D=3D SMMU_STAGE_1) { tt =3D select_tt(cfg, iova); if (!tt) { return; @@ -1151,7 +1162,7 @@ static void smmuv3_notify_iova(IOMMUMemoryRegion *mr, /* invalidate an asid/vmid/iova range tuple in all mr's */ static void smmuv3_inv_notifiers_iova(SMMUState *s, int asid, int vmid, dma_addr_t iova, uint8_t tg, - uint64_t num_pages) + uint64_t num_pages, int stage) { SMMUDevice *sdev; =20 @@ -1160,10 +1171,10 @@ static void smmuv3_inv_notifiers_iova(SMMUState *s,= int asid, int vmid, IOMMUNotifier *n; =20 trace_smmuv3_inv_notifiers_iova(mr->parent_obj.name, asid, vmid, - iova, tg, num_pages); + iova, tg, num_pages, stage); =20 IOMMU_NOTIFIER_FOREACH(n, mr) { - smmuv3_notify_iova(mr, n, asid, vmid, iova, tg, num_pages); + smmuv3_notify_iova(mr, n, asid, vmid, iova, tg, num_pages, sta= ge); } } } @@ -1194,7 +1205,7 @@ static void smmuv3_range_inval(SMMUState *s, Cmd *cmd= , SMMUStage stage) =20 if (!tg) { trace_smmuv3_range_inval(vmid, asid, addr, tg, 1, ttl, leaf, stage= ); - smmuv3_inv_notifiers_iova(s, asid, vmid, addr, tg, 1); + smmuv3_inv_notifiers_iova(s, asid, vmid, addr, tg, 1, stage); if (stage =3D=3D SMMU_STAGE_1) { smmu_iotlb_inv_iova(s, asid, vmid, addr, tg, 1, ttl); } else { @@ -1217,7 +1228,7 @@ static void smmuv3_range_inval(SMMUState *s, Cmd *cmd= , SMMUStage stage) num_pages =3D (mask + 1) >> granule; trace_smmuv3_range_inval(vmid, asid, addr, tg, num_pages, ttl, leaf, stage); - smmuv3_inv_notifiers_iova(s, asid, vmid, addr, tg, num_pages); + smmuv3_inv_notifiers_iova(s, asid, vmid, addr, tg, num_pages, stag= e); if (stage =3D=3D SMMU_STAGE_1) { smmu_iotlb_inv_iova(s, asid, vmid, addr, tg, num_pages, ttl); } else { diff --git a/hw/arm/trace-events b/hw/arm/trace-events index 593cc571da7..be6c8f720bc 100644 --- a/hw/arm/trace-events +++ b/hw/arm/trace-events @@ -55,7 +55,7 @@ smmuv3_cmdq_tlbi_s12_vmid(int vmid) "vmid=3D%d" smmuv3_config_cache_inv(uint32_t sid) "Config cache INV for sid=3D0x%x" smmuv3_notify_flag_add(const char *iommu) "ADD SMMUNotifier node for iommu= mr=3D%s" smmuv3_notify_flag_del(const char *iommu) "DEL SMMUNotifier node for iommu= mr=3D%s" -smmuv3_inv_notifiers_iova(const char *name, int asid, int vmid, uint64_t i= ova, uint8_t tg, uint64_t num_pages) "iommu mr=3D%s asid=3D%d vmid=3D%d iov= a=3D0x%"PRIx64" tg=3D%d num_pages=3D0x%"PRIx64 +smmuv3_inv_notifiers_iova(const char *name, int asid, int vmid, uint64_t i= ova, uint8_t tg, uint64_t num_pages, int stage) "iommu mr=3D%s asid=3D%d vm= id=3D%d iova=3D0x%"PRIx64" tg=3D%d num_pages=3D0x%"PRIx64" stage=3D%d" =20 # strongarm.c strongarm_uart_update_parameters(const char *label, int speed, char parity= , int data_bits, int stop_bits) "%s speed=3D%d parity=3D%c data=3D%d stop= =3D%d" --=20 2.34.1