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Thu, 18 Jul 2024 04:19:41 -0400 Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by orvoesa105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Jul 2024 01:19:38 -0700 Received: from spr-s2600bt.bj.intel.com ([10.240.192.127]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Jul 2024 01:19:35 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1721290779; x=1752826779; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=yIbrubkvEkSPS0YzQ6H3nvMCX3mqu3B1N5bY3N8r0+k=; b=hPb9UMTkbcjBGH3y8qoPdgWWXiUDll0p60bLbPYA1qDcW7+0ztPseCOe Q3PpwTIjiHgtmPuw46vSYMmbR/zAq4vhFxpsJFEYxRjCo/nT+GTJp0PYt 9jxxcp7UufhzJs8eyuPCFdFtP4t3YmGTrlg+0BZpvQ3FjmORspls7XVnv pirF6gYOD9bhXW7oWTDt88m3z6d3rH7B9cbIXhvMrs/21FPJ0/fKnKSRv cqDMFCe3xIf81KKvxMQzxhAfPUUWF/VXtbP40pc26yVGPz3wHay/YxpQp z7UlhBatbBJ9xPMCAqLfSA2MKDEaTx274V+/11auOF5TiQqMrcRCAd6fO w==; X-CSE-ConnectionGUID: 2p7MatdETkyi4keoLV6ykQ== X-CSE-MsgGUID: MB69EeMSQX68seiD1npXTQ== X-IronPort-AV: E=McAfee;i="6700,10204,11136"; a="29996150" X-IronPort-AV: E=Sophos;i="6.09,217,1716274800"; d="scan'208";a="29996150" X-CSE-ConnectionGUID: u3Bgen0jTOORmpoHSwywrw== X-CSE-MsgGUID: JjXWZoCvSgGDFzHVILc4HQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,217,1716274800"; d="scan'208";a="81717156" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, peterx@redhat.com, jasowang@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Zhenzhong Duan , Marcel Apfelbaum , Paolo Bonzini , Richard Henderson , Eduardo Habkost Subject: [PATCH v1 04/17] intel_iommu: Flush stage-2 cache in PADID-selective PASID-based iotlb invalidation Date: Thu, 18 Jul 2024 16:16:23 +0800 Message-Id: <20240718081636.879544-5-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240718081636.879544-1-zhenzhong.duan@intel.com> References: <20240718081636.879544-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.13; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1721290869328116600 Content-Type: text/plain; charset="utf-8" Per spec 6.5.2.4, PADID-selective PASID-based iotlb invalidation will flush stage-2 iotlb entries with matching domain id and pasid. With scalable modern mode introduced, guest could send PASID-selective PASID-based iotlb invalidation to flush both stage-1 and stage-2 entries. Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu_internal.h | 10 +++++ hw/i386/intel_iommu.c | 78 ++++++++++++++++++++++++++++++++++ 2 files changed, 88 insertions(+) diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h index 4e0331caba..f71fc91234 100644 --- a/hw/i386/intel_iommu_internal.h +++ b/hw/i386/intel_iommu_internal.h @@ -440,6 +440,16 @@ typedef union VTDInvDesc VTDInvDesc; (0x3ffff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM | VTD_SL_TM))= : \ (0x3ffff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM)) =20 +#define VTD_INV_DESC_PIOTLB_ALL_IN_PASID (2ULL << 4) +#define VTD_INV_DESC_PIOTLB_PSI_IN_PASID (3ULL << 4) + +#define VTD_INV_DESC_PIOTLB_RSVD_VAL0 0xfff000000000ffc0ULL +#define VTD_INV_DESC_PIOTLB_RSVD_VAL1 0xf80ULL + +#define VTD_INV_DESC_PIOTLB_PASID(val) (((val) >> 32) & 0xfffffULL) +#define VTD_INV_DESC_PIOTLB_DID(val) (((val) >> 16) & \ + VTD_DOMAIN_ID_MASK) + /* Information about page-selective IOTLB invalidate */ struct VTDIOTLBPageInvInfo { uint16_t domain_id; diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 40cbd4a0f4..075a27adac 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -2659,6 +2659,80 @@ static bool vtd_process_iotlb_desc(IntelIOMMUState *= s, VTDInvDesc *inv_desc) return true; } =20 +static gboolean vtd_hash_remove_by_pasid(gpointer key, gpointer value, + gpointer user_data) +{ + VTDIOTLBEntry *entry =3D (VTDIOTLBEntry *)value; + VTDIOTLBPageInvInfo *info =3D (VTDIOTLBPageInvInfo *)user_data; + + return ((entry->domain_id =3D=3D info->domain_id) && + (entry->pasid =3D=3D info->pasid)); +} + +static void vtd_piotlb_pasid_invalidate(IntelIOMMUState *s, + uint16_t domain_id, uint32_t pasid) +{ + VTDIOTLBPageInvInfo info; + VTDAddressSpace *vtd_as; + VTDContextEntry ce; + + info.domain_id =3D domain_id; + info.pasid =3D pasid; + + vtd_iommu_lock(s); + g_hash_table_foreach_remove(s->iotlb, vtd_hash_remove_by_pasid, + &info); + vtd_iommu_unlock(s); + + QLIST_FOREACH(vtd_as, &s->vtd_as_with_notifiers, next) { + if (!vtd_dev_to_context_entry(s, pci_bus_num(vtd_as->bus), + vtd_as->devfn, &ce) && + domain_id =3D=3D vtd_get_domain_id(s, &ce, vtd_as->pasid)) { + uint32_t rid2pasid =3D VTD_CE_GET_RID2PASID(&ce); + + if ((vtd_as->pasid !=3D PCI_NO_PASID || pasid !=3D rid2pasid) = && + vtd_as->pasid !=3D pasid) { + continue; + } + + if (!s->scalable_modern) { + vtd_address_space_sync(vtd_as); + } + } + } +} + +static bool vtd_process_piotlb_desc(IntelIOMMUState *s, + VTDInvDesc *inv_desc) +{ + uint16_t domain_id; + uint32_t pasid; + + if ((inv_desc->val[0] & VTD_INV_DESC_PIOTLB_RSVD_VAL0) || + (inv_desc->val[1] & VTD_INV_DESC_PIOTLB_RSVD_VAL1)) { + error_report_once("non-zero-field-in-piotlb_inv_desc hi: 0x%" PRIx= 64 + " lo: 0x%" PRIx64, inv_desc->val[1], inv_desc->val[0]); + return false; + } + + domain_id =3D VTD_INV_DESC_PIOTLB_DID(inv_desc->val[0]); + pasid =3D VTD_INV_DESC_PIOTLB_PASID(inv_desc->val[0]); + switch (inv_desc->val[0] & VTD_INV_DESC_IOTLB_G) { + case VTD_INV_DESC_PIOTLB_ALL_IN_PASID: + vtd_piotlb_pasid_invalidate(s, domain_id, pasid); + break; + + case VTD_INV_DESC_PIOTLB_PSI_IN_PASID: + break; + + default: + error_report_once("Invalid granularity in P-IOTLB desc hi: 0x%" PR= Ix64 + " lo: 0x%" PRIx64, inv_desc->val[1], inv_desc->val[0]); + return false; + } + return true; +} + static bool vtd_process_inv_iec_desc(IntelIOMMUState *s, VTDInvDesc *inv_desc) { @@ -2769,6 +2843,10 @@ static bool vtd_process_inv_desc(IntelIOMMUState *s) break; =20 case VTD_INV_DESC_PIOTLB: + trace_vtd_inv_desc("p-iotlb", inv_desc.val[1], inv_desc.val[0]); + if (!vtd_process_piotlb_desc(s, &inv_desc)) { + return false; + } break; =20 case VTD_INV_DESC_WAIT: --=20 2.34.1