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Thu, 18 Jul 2024 04:19:30 -0400 Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by orvoesa105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Jul 2024 01:19:25 -0700 Received: from spr-s2600bt.bj.intel.com ([10.240.192.127]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Jul 2024 01:19:21 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1721290768; x=1752826768; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=TRTaYDX3vvwEadIAz5kvOQCwOXFeSC1i6zzh/afdQDY=; b=WCnWjFlYZlA4JBtSLA5E7+w+UxP14+IF7KOJaDHTomQCYKomO6+sSowG NCFbae2p1XoFomRe3o2bs2gaU/x7kkEq+XeD8dpITzIoZECizCMGZSxrn HGpJ1EplhW8Firfe1czd6eMTb51U2xR33B1A26VgaRU2d06vhOGxiR4ts 6hvAIwI1XMlHHnrRGGKl1M46J53McoDIthF0K43CH5cT1L3oqPaV3l1Qe jwXvpeIy4JePpUn8mQ2VU68c3yt+ulutC2KYDh2L5piR89XK9NnNGZSCd TmTwbKVmEPW8cbGC/TtqkLnBLGFTkOvFmCT2FPNM5EfweZdAK6vpbNld6 g==; X-CSE-ConnectionGUID: qJVKIZG1TK+dwTNw9Ju9cA== X-CSE-MsgGUID: 16sHwc+sRBmq2tj+mqO5FQ== X-IronPort-AV: E=McAfee;i="6700,10204,11136"; a="29996126" X-IronPort-AV: E=Sophos;i="6.09,217,1716274800"; d="scan'208";a="29996126" X-CSE-ConnectionGUID: LNBnZGX6QIyBC+VqeXMKSg== X-CSE-MsgGUID: aRQ9uD1DQpSAIfGkNa/9Dw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,217,1716274800"; d="scan'208";a="81717077" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, peterx@redhat.com, jasowang@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Yu Zhang , Zhenzhong Duan , Paolo Bonzini , Richard Henderson , Eduardo Habkost , Marcel Apfelbaum Subject: [PATCH v1 01/17] intel_iommu: Use the latest fault reasons defined by spec Date: Thu, 18 Jul 2024 16:16:20 +0800 Message-Id: <20240718081636.879544-2-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240718081636.879544-1-zhenzhong.duan@intel.com> References: <20240718081636.879544-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.13; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1721290869355116600 Content-Type: text/plain; charset="utf-8" From: Yu Zhang Spec revision 3.0 or above defines more detailed fault reasons for scalable mode. So introduce them into emulation code, see spec section 7.1.2 for details. Note spec revision has no relation with VERSION register, Guest kernel should not use that register to judge what features are supported. Instead cap/ecap bits should be checked. Signed-off-by: Yu Zhang Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu_internal.h | 9 ++++++++- hw/i386/intel_iommu.c | 25 ++++++++++++++++--------- 2 files changed, 24 insertions(+), 10 deletions(-) diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h index f8cf99bddf..c0ca7b372f 100644 --- a/hw/i386/intel_iommu_internal.h +++ b/hw/i386/intel_iommu_internal.h @@ -311,7 +311,14 @@ typedef enum VTDFaultReason { * request while disabled */ VTD_FR_IR_SID_ERR =3D 0x26, /* Invalid Source-ID */ =20 - VTD_FR_PASID_TABLE_INV =3D 0x58, /*Invalid PASID table entry */ + /* PASID directory entry access failure */ + VTD_FR_PASID_DIR_ACCESS_ERR =3D 0x50, + /* The Present(P) field of pasid directory entry is 0 */ + VTD_FR_PASID_DIR_ENTRY_P =3D 0x51, + VTD_FR_PASID_TABLE_ACCESS_ERR =3D 0x58, /* PASID table entry access fa= ilure */ + /* The Present(P) field of pasid table entry is 0 */ + VTD_FR_PASID_ENTRY_P =3D 0x59, + VTD_FR_PASID_TABLE_ENTRY_INV =3D 0x5b, /*Invalid PASID table entry */ =20 /* Output address in the interrupt address range for scalable mode */ VTD_FR_SM_INTERRUPT_ADDR =3D 0x87, diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 37c21a0aec..e65f5b29a5 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -796,7 +796,7 @@ static int vtd_get_pdire_from_pdir_table(dma_addr_t pas= id_dir_base, addr =3D pasid_dir_base + index * entry_size; if (dma_memory_read(&address_space_memory, addr, pdire, entry_size, MEMTXATTRS_UNSPECIFIED)) { - return -VTD_FR_PASID_TABLE_INV; + return -VTD_FR_PASID_DIR_ACCESS_ERR; } =20 pdire->val =3D le64_to_cpu(pdire->val); @@ -814,6 +814,7 @@ static int vtd_get_pe_in_pasid_leaf_table(IntelIOMMUSta= te *s, dma_addr_t addr, VTDPASIDEntry *pe) { + uint8_t pgtt; uint32_t index; dma_addr_t entry_size; X86IOMMUState *x86_iommu =3D X86_IOMMU_DEVICE(s); @@ -823,7 +824,7 @@ static int vtd_get_pe_in_pasid_leaf_table(IntelIOMMUSta= te *s, addr =3D addr + index * entry_size; if (dma_memory_read(&address_space_memory, addr, pe, entry_size, MEMTXATTRS_UNSPECIFIED)) { - return -VTD_FR_PASID_TABLE_INV; + return -VTD_FR_PASID_TABLE_ACCESS_ERR; } for (size_t i =3D 0; i < ARRAY_SIZE(pe->val); i++) { pe->val[i] =3D le64_to_cpu(pe->val[i]); @@ -831,11 +832,13 @@ static int vtd_get_pe_in_pasid_leaf_table(IntelIOMMUS= tate *s, =20 /* Do translation type check */ if (!vtd_pe_type_check(x86_iommu, pe)) { - return -VTD_FR_PASID_TABLE_INV; + return -VTD_FR_PASID_TABLE_ENTRY_INV; } =20 - if (!vtd_is_level_supported(s, VTD_PE_GET_LEVEL(pe))) { - return -VTD_FR_PASID_TABLE_INV; + pgtt =3D VTD_PE_GET_TYPE(pe); + if (pgtt =3D=3D VTD_SM_PASID_ENTRY_SLT && + !vtd_is_level_supported(s, VTD_PE_GET_LEVEL(pe))) { + return -VTD_FR_PASID_TABLE_ENTRY_INV; } =20 return 0; @@ -876,7 +879,7 @@ static int vtd_get_pe_from_pasid_table(IntelIOMMUState = *s, } =20 if (!vtd_pdire_present(&pdire)) { - return -VTD_FR_PASID_TABLE_INV; + return -VTD_FR_PASID_DIR_ENTRY_P; } =20 ret =3D vtd_get_pe_from_pdire(s, pasid, &pdire, pe); @@ -885,7 +888,7 @@ static int vtd_get_pe_from_pasid_table(IntelIOMMUState = *s, } =20 if (!vtd_pe_present(pe)) { - return -VTD_FR_PASID_TABLE_INV; + return -VTD_FR_PASID_ENTRY_P; } =20 return 0; @@ -938,7 +941,7 @@ static int vtd_ce_get_pasid_fpd(IntelIOMMUState *s, } =20 if (!vtd_pdire_present(&pdire)) { - return -VTD_FR_PASID_TABLE_INV; + return -VTD_FR_PASID_DIR_ENTRY_P; } =20 /* @@ -1795,7 +1798,11 @@ static const bool vtd_qualified_faults[] =3D { [VTD_FR_ROOT_ENTRY_RSVD] =3D false, [VTD_FR_PAGING_ENTRY_RSVD] =3D true, [VTD_FR_CONTEXT_ENTRY_TT] =3D true, - [VTD_FR_PASID_TABLE_INV] =3D false, + [VTD_FR_PASID_DIR_ACCESS_ERR] =3D false, + [VTD_FR_PASID_DIR_ENTRY_P] =3D true, + [VTD_FR_PASID_TABLE_ACCESS_ERR] =3D false, + [VTD_FR_PASID_ENTRY_P] =3D true, + [VTD_FR_PASID_TABLE_ENTRY_INV] =3D true, [VTD_FR_SM_INTERRUPT_ADDR] =3D true, [VTD_FR_MAX] =3D false, }; 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a="29996130" X-IronPort-AV: E=Sophos;i="6.09,217,1716274800"; d="scan'208";a="29996130" X-CSE-ConnectionGUID: RaPN0r9pTrSgk6aEj59bsQ== X-CSE-MsgGUID: 6ptezVOMTmug0kcBJr2mxw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,217,1716274800"; d="scan'208";a="81717096" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, peterx@redhat.com, jasowang@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Zhenzhong Duan , Paolo Bonzini , Richard Henderson , Eduardo Habkost , Marcel Apfelbaum Subject: [PATCH v1 02/17] intel_iommu: Make pasid entry type check accurate Date: Thu, 18 Jul 2024 16:16:21 +0800 Message-Id: <20240718081636.879544-3-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240718081636.879544-1-zhenzhong.duan@intel.com> References: <20240718081636.879544-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.13; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1721290899217116601 Content-Type: text/plain; charset="utf-8" When guest configures Nested Translation(011b) or First-stage Translation o= nly (001b), type check passed unaccurately. Fails the type check in those cases as their simulation isn't supported yet. Fixes: fb43cf739e1 ("intel_iommu: scalable mode emulation") Suggested-by: Yi Liu Signed-off-by: Zhenzhong Duan Reviewed-by: Cl=C3=A9ment Mathieu--Drif --- hw/i386/intel_iommu.c | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index e65f5b29a5..1cff8b00ae 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -759,20 +759,16 @@ static inline bool vtd_pe_type_check(X86IOMMUState *x= 86_iommu, VTDPASIDEntry *pe) { switch (VTD_PE_GET_TYPE(pe)) { - case VTD_SM_PASID_ENTRY_FLT: case VTD_SM_PASID_ENTRY_SLT: - case VTD_SM_PASID_ENTRY_NESTED: - break; + return true; case VTD_SM_PASID_ENTRY_PT: - if (!x86_iommu->pt_supported) { - return false; - } - break; + return x86_iommu->pt_supported; + case VTD_SM_PASID_ENTRY_FLT: + case VTD_SM_PASID_ENTRY_NESTED: default: /* Unknown type */ return false; } - return true; } =20 static inline bool vtd_pdire_present(VTDPASIDDirEntry *pdire) --=20 2.34.1 From nobody Mon Sep 16 19:12:33 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 18 Jul 2024 04:19:37 -0400 Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by orvoesa105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Jul 2024 01:19:34 -0700 Received: from spr-s2600bt.bj.intel.com ([10.240.192.127]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Jul 2024 01:19:30 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1721290775; x=1752826775; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=HGlgmPL0tpzaQnQi2F+oTSTTGoGfTxoXVwUJvqqqnZ0=; b=AADTiZl4AqfsUE74HXXvObMd4Kh/x6KEQpRci98PXZSmD6uD3llbbbXD lm/SJQ0RHC+N8svtjwH/eefpKg9HGqP0QbkAcppvX5D5meWmMV2P/3jsQ rnx0InOE3vMvktOSoUazBz2C0iS2FISUDyysgGCrWiZly8xkCM7lXkrAQ qFczK/4mnQPOA+Soh8CpebxUXlXs2pq46qDXsC2lmv37Ku7cYVUwTCf7u mraGadq6h0yndA46BoOG8WIsWxV8ITCWZHtKNPv3Oi/QH245E4ojyDEvi bnZQe1DbnzmNV1jK2h1V6fwTDPYrfWXrWh4h4a7R+Zh72OPfgmIW+OhGN w==; X-CSE-ConnectionGUID: +ToJlRkQS4WueFSgBFc5mA== X-CSE-MsgGUID: EBF13lZTRCiEdSkEYNwf8A== X-IronPort-AV: E=McAfee;i="6700,10204,11136"; a="29996139" X-IronPort-AV: E=Sophos;i="6.09,217,1716274800"; d="scan'208";a="29996139" X-CSE-ConnectionGUID: EAgaSNRPRGG9mBOSi9b4lw== X-CSE-MsgGUID: elt6DWCOT325f/JKCqyg/Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,217,1716274800"; d="scan'208";a="81717122" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, peterx@redhat.com, jasowang@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Zhenzhong Duan , Paolo Bonzini , Richard Henderson , Eduardo Habkost , Marcel Apfelbaum Subject: [PATCH v1 03/17] intel_iommu: Add a placeholder variable for scalable modern mode Date: Thu, 18 Jul 2024 16:16:22 +0800 Message-Id: <20240718081636.879544-4-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240718081636.879544-1-zhenzhong.duan@intel.com> References: <20240718081636.879544-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.13; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1721290901269116600 Content-Type: text/plain; charset="utf-8" Add an new element scalable_mode in IntelIOMMUState to mark scalable modern mode, this element will be exposed as an intel_iommu property finally. For now, it's only a placehholder and used for cap/ecap initialization, compatibility check and block host device passthrough until nesting is supported. Signed-off-by: Yi Liu Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu_internal.h | 2 ++ include/hw/i386/intel_iommu.h | 1 + hw/i386/intel_iommu.c | 34 +++++++++++++++++++++++----------- 3 files changed, 26 insertions(+), 11 deletions(-) diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h index c0ca7b372f..4e0331caba 100644 --- a/hw/i386/intel_iommu_internal.h +++ b/hw/i386/intel_iommu_internal.h @@ -195,6 +195,7 @@ #define VTD_ECAP_PASID (1ULL << 40) #define VTD_ECAP_SMTS (1ULL << 43) #define VTD_ECAP_SLTS (1ULL << 46) +#define VTD_ECAP_FLTS (1ULL << 47) =20 /* CAP_REG */ /* (offset >> 4) << 24 */ @@ -211,6 +212,7 @@ #define VTD_CAP_SLLPS ((1ULL << 34) | (1ULL << 35)) #define VTD_CAP_DRAIN_WRITE (1ULL << 54) #define VTD_CAP_DRAIN_READ (1ULL << 55) +#define VTD_CAP_FS1GP (1ULL << 56) #define VTD_CAP_DRAIN (VTD_CAP_DRAIN_READ | VTD_CAP_DRAIN_WR= ITE) #define VTD_CAP_CM (1ULL << 7) #define VTD_PASID_ID_SHIFT 20 diff --git a/include/hw/i386/intel_iommu.h b/include/hw/i386/intel_iommu.h index 1eb05c29fc..788ed42477 100644 --- a/include/hw/i386/intel_iommu.h +++ b/include/hw/i386/intel_iommu.h @@ -262,6 +262,7 @@ struct IntelIOMMUState { =20 bool caching_mode; /* RO - is cap CM enabled? */ bool scalable_mode; /* RO - is Scalable Mode supported? */ + bool scalable_modern; /* RO - is modern SM supported? */ bool snoop_control; /* RO - is SNP filed supported? */ =20 dma_addr_t root; /* Current root table pointer */ diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 1cff8b00ae..40cbd4a0f4 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -755,16 +755,20 @@ static inline bool vtd_is_level_supported(IntelIOMMUS= tate *s, uint32_t level) } =20 /* Return true if check passed, otherwise false */ -static inline bool vtd_pe_type_check(X86IOMMUState *x86_iommu, - VTDPASIDEntry *pe) +static inline bool vtd_pe_type_check(IntelIOMMUState *s, VTDPASIDEntry *pe) { + X86IOMMUState *x86_iommu =3D X86_IOMMU_DEVICE(s); + switch (VTD_PE_GET_TYPE(pe)) { + case VTD_SM_PASID_ENTRY_FLT: + return s->scalable_modern; case VTD_SM_PASID_ENTRY_SLT: - return true; + return !s->scalable_modern; + case VTD_SM_PASID_ENTRY_NESTED: + /* Not support NESTED page table type yet */ + return false; case VTD_SM_PASID_ENTRY_PT: return x86_iommu->pt_supported; - case VTD_SM_PASID_ENTRY_FLT: - case VTD_SM_PASID_ENTRY_NESTED: default: /* Unknown type */ return false; @@ -813,7 +817,6 @@ static int vtd_get_pe_in_pasid_leaf_table(IntelIOMMUSta= te *s, uint8_t pgtt; uint32_t index; dma_addr_t entry_size; - X86IOMMUState *x86_iommu =3D X86_IOMMU_DEVICE(s); =20 index =3D VTD_PASID_TABLE_INDEX(pasid); entry_size =3D VTD_PASID_ENTRY_SIZE; @@ -827,7 +830,7 @@ static int vtd_get_pe_in_pasid_leaf_table(IntelIOMMUSta= te *s, } =20 /* Do translation type check */ - if (!vtd_pe_type_check(x86_iommu, pe)) { + if (!vtd_pe_type_check(s, pe)) { return -VTD_FR_PASID_TABLE_ENTRY_INV; } =20 @@ -3861,7 +3864,13 @@ static bool vtd_check_hiod(IntelIOMMUState *s, HostI= OMMUDevice *hiod, return false; } =20 - return true; + if (!s->scalable_modern) { + /* All checks requested by VTD non-modern mode pass */ + return true; + } + + error_setg(errp, "host device is unsupported in scalable modern mode y= et"); + return false; } =20 static bool vtd_dev_set_iommu_device(PCIBus *bus, void *opaque, int devfn, @@ -4084,7 +4093,10 @@ static void vtd_cap_init(IntelIOMMUState *s) } =20 /* TODO: read cap/ecap from host to decide which cap to be exposed. */ - if (s->scalable_mode) { + if (s->scalable_modern) { + s->ecap |=3D VTD_ECAP_SMTS | VTD_ECAP_FLTS; + s->cap |=3D VTD_CAP_FS1GP; + } else if (s->scalable_mode) { s->ecap |=3D VTD_ECAP_SMTS | VTD_ECAP_SRS | VTD_ECAP_SLTS; } =20 @@ -4251,9 +4263,9 @@ static bool vtd_decide_config(IntelIOMMUState *s, Err= or **errp) } } =20 - /* Currently only address widths supported are 39 and 48 bits */ if ((s->aw_bits !=3D VTD_HOST_AW_39BIT) && - (s->aw_bits !=3D VTD_HOST_AW_48BIT)) { + (s->aw_bits !=3D VTD_HOST_AW_48BIT) && + !s->scalable_modern) { error_setg(errp, "Supported values for aw-bits are: %d, %d", VTD_HOST_AW_39BIT, VTD_HOST_AW_48BIT); return false; --=20 2.34.1 From nobody Mon Sep 16 19:12:33 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 18 Jul 2024 04:19:41 -0400 Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by orvoesa105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Jul 2024 01:19:38 -0700 Received: from spr-s2600bt.bj.intel.com ([10.240.192.127]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Jul 2024 01:19:35 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1721290779; x=1752826779; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=yIbrubkvEkSPS0YzQ6H3nvMCX3mqu3B1N5bY3N8r0+k=; b=hPb9UMTkbcjBGH3y8qoPdgWWXiUDll0p60bLbPYA1qDcW7+0ztPseCOe Q3PpwTIjiHgtmPuw46vSYMmbR/zAq4vhFxpsJFEYxRjCo/nT+GTJp0PYt 9jxxcp7UufhzJs8eyuPCFdFtP4t3YmGTrlg+0BZpvQ3FjmORspls7XVnv pirF6gYOD9bhXW7oWTDt88m3z6d3rH7B9cbIXhvMrs/21FPJ0/fKnKSRv cqDMFCe3xIf81KKvxMQzxhAfPUUWF/VXtbP40pc26yVGPz3wHay/YxpQp z7UlhBatbBJ9xPMCAqLfSA2MKDEaTx274V+/11auOF5TiQqMrcRCAd6fO w==; X-CSE-ConnectionGUID: 2p7MatdETkyi4keoLV6ykQ== X-CSE-MsgGUID: MB69EeMSQX68seiD1npXTQ== X-IronPort-AV: E=McAfee;i="6700,10204,11136"; a="29996150" X-IronPort-AV: E=Sophos;i="6.09,217,1716274800"; d="scan'208";a="29996150" X-CSE-ConnectionGUID: u3Bgen0jTOORmpoHSwywrw== X-CSE-MsgGUID: JjXWZoCvSgGDFzHVILc4HQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,217,1716274800"; d="scan'208";a="81717156" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, peterx@redhat.com, jasowang@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Zhenzhong Duan , Marcel Apfelbaum , Paolo Bonzini , Richard Henderson , Eduardo Habkost Subject: [PATCH v1 04/17] intel_iommu: Flush stage-2 cache in PADID-selective PASID-based iotlb invalidation Date: Thu, 18 Jul 2024 16:16:23 +0800 Message-Id: <20240718081636.879544-5-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240718081636.879544-1-zhenzhong.duan@intel.com> References: <20240718081636.879544-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.13; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1721290869328116600 Content-Type: text/plain; charset="utf-8" Per spec 6.5.2.4, PADID-selective PASID-based iotlb invalidation will flush stage-2 iotlb entries with matching domain id and pasid. With scalable modern mode introduced, guest could send PASID-selective PASID-based iotlb invalidation to flush both stage-1 and stage-2 entries. Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu_internal.h | 10 +++++ hw/i386/intel_iommu.c | 78 ++++++++++++++++++++++++++++++++++ 2 files changed, 88 insertions(+) diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h index 4e0331caba..f71fc91234 100644 --- a/hw/i386/intel_iommu_internal.h +++ b/hw/i386/intel_iommu_internal.h @@ -440,6 +440,16 @@ typedef union VTDInvDesc VTDInvDesc; (0x3ffff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM | VTD_SL_TM))= : \ (0x3ffff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM)) =20 +#define VTD_INV_DESC_PIOTLB_ALL_IN_PASID (2ULL << 4) +#define VTD_INV_DESC_PIOTLB_PSI_IN_PASID (3ULL << 4) + +#define VTD_INV_DESC_PIOTLB_RSVD_VAL0 0xfff000000000ffc0ULL +#define VTD_INV_DESC_PIOTLB_RSVD_VAL1 0xf80ULL + +#define VTD_INV_DESC_PIOTLB_PASID(val) (((val) >> 32) & 0xfffffULL) +#define VTD_INV_DESC_PIOTLB_DID(val) (((val) >> 16) & \ + VTD_DOMAIN_ID_MASK) + /* Information about page-selective IOTLB invalidate */ struct VTDIOTLBPageInvInfo { uint16_t domain_id; diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 40cbd4a0f4..075a27adac 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -2659,6 +2659,80 @@ static bool vtd_process_iotlb_desc(IntelIOMMUState *= s, VTDInvDesc *inv_desc) return true; } =20 +static gboolean vtd_hash_remove_by_pasid(gpointer key, gpointer value, + gpointer user_data) +{ + VTDIOTLBEntry *entry =3D (VTDIOTLBEntry *)value; + VTDIOTLBPageInvInfo *info =3D (VTDIOTLBPageInvInfo *)user_data; + + return ((entry->domain_id =3D=3D info->domain_id) && + (entry->pasid =3D=3D info->pasid)); +} + +static void vtd_piotlb_pasid_invalidate(IntelIOMMUState *s, + uint16_t domain_id, uint32_t pasid) +{ + VTDIOTLBPageInvInfo info; + VTDAddressSpace *vtd_as; + VTDContextEntry ce; + + info.domain_id =3D domain_id; + info.pasid =3D pasid; + + vtd_iommu_lock(s); + g_hash_table_foreach_remove(s->iotlb, vtd_hash_remove_by_pasid, + &info); + vtd_iommu_unlock(s); + + QLIST_FOREACH(vtd_as, &s->vtd_as_with_notifiers, next) { + if (!vtd_dev_to_context_entry(s, pci_bus_num(vtd_as->bus), + vtd_as->devfn, &ce) && + domain_id =3D=3D vtd_get_domain_id(s, &ce, vtd_as->pasid)) { + uint32_t rid2pasid =3D VTD_CE_GET_RID2PASID(&ce); + + if ((vtd_as->pasid !=3D PCI_NO_PASID || pasid !=3D rid2pasid) = && + vtd_as->pasid !=3D pasid) { + continue; + } + + if (!s->scalable_modern) { + vtd_address_space_sync(vtd_as); + } + } + } +} + +static bool vtd_process_piotlb_desc(IntelIOMMUState *s, + VTDInvDesc *inv_desc) +{ + uint16_t domain_id; + uint32_t pasid; + + if ((inv_desc->val[0] & VTD_INV_DESC_PIOTLB_RSVD_VAL0) || + (inv_desc->val[1] & VTD_INV_DESC_PIOTLB_RSVD_VAL1)) { + error_report_once("non-zero-field-in-piotlb_inv_desc hi: 0x%" PRIx= 64 + " lo: 0x%" PRIx64, inv_desc->val[1], inv_desc->val[0]); + return false; + } + + domain_id =3D VTD_INV_DESC_PIOTLB_DID(inv_desc->val[0]); + pasid =3D VTD_INV_DESC_PIOTLB_PASID(inv_desc->val[0]); + switch (inv_desc->val[0] & VTD_INV_DESC_IOTLB_G) { + case VTD_INV_DESC_PIOTLB_ALL_IN_PASID: + vtd_piotlb_pasid_invalidate(s, domain_id, pasid); + break; + + case VTD_INV_DESC_PIOTLB_PSI_IN_PASID: + break; + + default: + error_report_once("Invalid granularity in P-IOTLB desc hi: 0x%" PR= Ix64 + " lo: 0x%" PRIx64, inv_desc->val[1], inv_desc->val[0]); + return false; + } + return true; +} + static bool vtd_process_inv_iec_desc(IntelIOMMUState *s, VTDInvDesc *inv_desc) { @@ -2769,6 +2843,10 @@ static bool vtd_process_inv_desc(IntelIOMMUState *s) break; =20 case VTD_INV_DESC_PIOTLB: + trace_vtd_inv_desc("p-iotlb", inv_desc.val[1], inv_desc.val[0]); + if (!vtd_process_piotlb_desc(s, &inv_desc)) { + return false; + } break; =20 case VTD_INV_DESC_WAIT: --=20 2.34.1 From nobody Mon Sep 16 19:12:33 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1721290902; cv=none; d=zohomail.com; s=zohoarc; b=Tlvz1rJbpV6rkwU1hTuzBceSimjY9KShVDdwwLv9hq/xcLb0zT+FKWSnUwKuKS4xbofJnOUd3tR1ji5g37QUP4a3TSOsTLuSbjJAaQYsOsS5Xd59joF2i5X85VJFQL/gC0Z2jv19vXJnvHxeT/rG1pvJgbqQZz/LNzLNZGB7vLo= ARC-Message-Signature: i=1; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.13; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1721290903366116600 From: Yi Liu Because we will support both FST(a.k.a, FLT) and SST(a.k.a, SLT) translatio= n, rename variable and functions from slpte to pte whenever possible. But some are SST only, they are renamed with sl_ prefix. Signed-off-by: Yi Liu Co-developed-by: Cl=C3=A9ment Mathieu--Drif Signed-off-by: Cl=C3=A9ment Mathieu--Drif Signed-off-by: Yi Sun Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu_internal.h | 24 +++--- include/hw/i386/intel_iommu.h | 2 +- hw/i386/intel_iommu.c | 129 +++++++++++++++++---------------- 3 files changed, 78 insertions(+), 77 deletions(-) diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h index f71fc91234..1875c2ddd6 100644 --- a/hw/i386/intel_iommu_internal.h +++ b/hw/i386/intel_iommu_internal.h @@ -536,24 +536,24 @@ typedef struct VTDRootEntry VTDRootEntry; /* Second Level Page Translation Pointer*/ #define VTD_SM_PASID_ENTRY_SLPTPTR (~0xfffULL) =20 -/* Paging Structure common */ -#define VTD_SL_PT_PAGE_SIZE_MASK (1ULL << 7) -/* Bits to decide the offset for each level */ -#define VTD_SL_LEVEL_BITS 9 - /* Second Level Paging Structure */ -#define VTD_SL_PML4_LEVEL 4 -#define VTD_SL_PDP_LEVEL 3 -#define VTD_SL_PD_LEVEL 2 -#define VTD_SL_PT_LEVEL 1 -#define VTD_SL_PT_ENTRY_NR 512 - /* Masks for Second Level Paging Entry */ #define VTD_SL_RW_MASK 3ULL #define VTD_SL_R 1ULL #define VTD_SL_W (1ULL << 1) -#define VTD_SL_PT_BASE_ADDR_MASK(aw) (~(VTD_PAGE_SIZE - 1) & VTD_HAW_MASK(= aw)) #define VTD_SL_IGN_COM 0xbff0000000000000ULL #define VTD_SL_TM (1ULL << 62) =20 +/* Common for both First Level and Second Level */ +#define VTD_PML4_LEVEL 4 +#define VTD_PDP_LEVEL 3 +#define VTD_PD_LEVEL 2 +#define VTD_PT_LEVEL 1 +#define VTD_PT_ENTRY_NR 512 +#define VTD_PT_PAGE_SIZE_MASK (1ULL << 7) +#define VTD_PT_BASE_ADDR_MASK(aw) (~(VTD_PAGE_SIZE - 1) & VTD_HAW_MASK(aw)) + +/* Bits to decide the offset for each level */ +#define VTD_LEVEL_BITS 9 + #endif diff --git a/include/hw/i386/intel_iommu.h b/include/hw/i386/intel_iommu.h index 788ed42477..fe9057c50d 100644 --- a/include/hw/i386/intel_iommu.h +++ b/include/hw/i386/intel_iommu.h @@ -152,7 +152,7 @@ struct VTDIOTLBEntry { uint64_t gfn; uint16_t domain_id; uint32_t pasid; - uint64_t slpte; + uint64_t pte; uint64_t mask; uint8_t access_flags; }; diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 075a27adac..94f6532935 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -48,7 +48,8 @@ =20 /* pe operations */ #define VTD_PE_GET_TYPE(pe) ((pe)->val[0] & VTD_SM_PASID_ENTRY_PGTT) -#define VTD_PE_GET_LEVEL(pe) (2 + (((pe)->val[0] >> 2) & VTD_SM_PASID_ENTR= Y_AW)) +#define VTD_PE_GET_SL_LEVEL(pe) \ + (2 + (((pe)->val[0] >> 2) & VTD_SM_PASID_ENTRY_AW)) =20 /* * PCI bus number (or SID) is not reliable since the device is usaully @@ -284,15 +285,15 @@ static gboolean vtd_hash_remove_by_domain(gpointer ke= y, gpointer value, } =20 /* The shift of an addr for a certain level of paging structure */ -static inline uint32_t vtd_slpt_level_shift(uint32_t level) +static inline uint32_t vtd_pt_level_shift(uint32_t level) { assert(level !=3D 0); - return VTD_PAGE_SHIFT_4K + (level - 1) * VTD_SL_LEVEL_BITS; + return VTD_PAGE_SHIFT_4K + (level - 1) * VTD_LEVEL_BITS; } =20 -static inline uint64_t vtd_slpt_level_page_mask(uint32_t level) +static inline uint64_t vtd_pt_level_page_mask(uint32_t level) { - return ~((1ULL << vtd_slpt_level_shift(level)) - 1); + return ~((1ULL << vtd_pt_level_shift(level)) - 1); } =20 static gboolean vtd_hash_remove_by_page(gpointer key, gpointer value, @@ -349,7 +350,7 @@ static void vtd_reset_caches(IntelIOMMUState *s) =20 static uint64_t vtd_get_iotlb_gfn(hwaddr addr, uint32_t level) { - return (addr & vtd_slpt_level_page_mask(level)) >> VTD_PAGE_SHIFT_4K; + return (addr & vtd_pt_level_page_mask(level)) >> VTD_PAGE_SHIFT_4K; } =20 /* Must be called with IOMMU lock held */ @@ -360,7 +361,7 @@ static VTDIOTLBEntry *vtd_lookup_iotlb(IntelIOMMUState = *s, uint16_t source_id, VTDIOTLBEntry *entry; int level; =20 - for (level =3D VTD_SL_PT_LEVEL; level < VTD_SL_PML4_LEVEL; level++) { + for (level =3D VTD_PT_LEVEL; level < VTD_PML4_LEVEL; level++) { key.gfn =3D vtd_get_iotlb_gfn(addr, level); key.level =3D level; key.sid =3D source_id; @@ -377,7 +378,7 @@ out: =20 /* Must be with IOMMU lock held */ static void vtd_update_iotlb(IntelIOMMUState *s, uint16_t source_id, - uint16_t domain_id, hwaddr addr, uint64_t slp= te, + uint16_t domain_id, hwaddr addr, uint64_t pte, uint8_t access_flags, uint32_t level, uint32_t pasid) { @@ -385,7 +386,7 @@ static void vtd_update_iotlb(IntelIOMMUState *s, uint16= _t source_id, struct vtd_iotlb_key *key =3D g_malloc(sizeof(*key)); uint64_t gfn =3D vtd_get_iotlb_gfn(addr, level); =20 - trace_vtd_iotlb_page_update(source_id, addr, slpte, domain_id); + trace_vtd_iotlb_page_update(source_id, addr, pte, domain_id); if (g_hash_table_size(s->iotlb) >=3D VTD_IOTLB_MAX_SIZE) { trace_vtd_iotlb_reset("iotlb exceeds size limit"); vtd_reset_iotlb_locked(s); @@ -393,9 +394,9 @@ static void vtd_update_iotlb(IntelIOMMUState *s, uint16= _t source_id, =20 entry->gfn =3D gfn; entry->domain_id =3D domain_id; - entry->slpte =3D slpte; + entry->pte =3D pte; entry->access_flags =3D access_flags; - entry->mask =3D vtd_slpt_level_page_mask(level); + entry->mask =3D vtd_pt_level_page_mask(level); entry->pasid =3D pasid; =20 key->gfn =3D gfn; @@ -710,32 +711,32 @@ static inline dma_addr_t vtd_ce_get_slpt_base(VTDCont= extEntry *ce) return ce->lo & VTD_CONTEXT_ENTRY_SLPTPTR; } =20 -static inline uint64_t vtd_get_slpte_addr(uint64_t slpte, uint8_t aw) +static inline uint64_t vtd_get_pte_addr(uint64_t pte, uint8_t aw) { - return slpte & VTD_SL_PT_BASE_ADDR_MASK(aw); + return pte & VTD_PT_BASE_ADDR_MASK(aw); } =20 /* Whether the pte indicates the address of the page frame */ -static inline bool vtd_is_last_slpte(uint64_t slpte, uint32_t level) +static inline bool vtd_is_last_pte(uint64_t pte, uint32_t level) { - return level =3D=3D VTD_SL_PT_LEVEL || (slpte & VTD_SL_PT_PAGE_SIZE_MA= SK); + return level =3D=3D VTD_PT_LEVEL || (pte & VTD_PT_PAGE_SIZE_MASK); } =20 -/* Get the content of a spte located in @base_addr[@index] */ -static uint64_t vtd_get_slpte(dma_addr_t base_addr, uint32_t index) +/* Get the content of a pte located in @base_addr[@index] */ +static uint64_t vtd_get_pte(dma_addr_t base_addr, uint32_t index) { - uint64_t slpte; + uint64_t pte; =20 - assert(index < VTD_SL_PT_ENTRY_NR); + assert(index < VTD_PT_ENTRY_NR); =20 if (dma_memory_read(&address_space_memory, - base_addr + index * sizeof(slpte), - &slpte, sizeof(slpte), MEMTXATTRS_UNSPECIFIED)) { - slpte =3D (uint64_t)-1; - return slpte; + base_addr + index * sizeof(pte), + &pte, sizeof(pte), MEMTXATTRS_UNSPECIFIED)) { + pte =3D (uint64_t)-1; + return pte; } - slpte =3D le64_to_cpu(slpte); - return slpte; + pte =3D le64_to_cpu(pte); + return pte; } =20 /* Given an iova and the level of paging structure, return the offset @@ -743,12 +744,12 @@ static uint64_t vtd_get_slpte(dma_addr_t base_addr, u= int32_t index) */ static inline uint32_t vtd_iova_level_offset(uint64_t iova, uint32_t level) { - return (iova >> vtd_slpt_level_shift(level)) & - ((1ULL << VTD_SL_LEVEL_BITS) - 1); + return (iova >> vtd_pt_level_shift(level)) & + ((1ULL << VTD_LEVEL_BITS) - 1); } =20 /* Check Capability Register to see if the @level of page-table is support= ed */ -static inline bool vtd_is_level_supported(IntelIOMMUState *s, uint32_t lev= el) +static inline bool vtd_is_sl_level_supported(IntelIOMMUState *s, uint32_t = level) { return VTD_CAP_SAGAW_MASK & s->cap & (1ULL << (level - 2 + VTD_CAP_SAGAW_SHIFT)); @@ -836,7 +837,7 @@ static int vtd_get_pe_in_pasid_leaf_table(IntelIOMMUSta= te *s, =20 pgtt =3D VTD_PE_GET_TYPE(pe); if (pgtt =3D=3D VTD_SM_PASID_ENTRY_SLT && - !vtd_is_level_supported(s, VTD_PE_GET_LEVEL(pe))) { + !vtd_is_sl_level_supported(s, VTD_PE_GET_SL_LEVEL(pe))) { return -VTD_FR_PASID_TABLE_ENTRY_INV; } =20 @@ -975,7 +976,7 @@ static uint32_t vtd_get_iova_level(IntelIOMMUState *s, =20 if (s->root_scalable) { vtd_ce_get_rid2pasid_entry(s, ce, &pe, pasid); - return VTD_PE_GET_LEVEL(&pe); + return VTD_PE_GET_SL_LEVEL(&pe); } =20 return vtd_ce_get_level(ce); @@ -1043,9 +1044,9 @@ static inline uint64_t vtd_iova_limit(IntelIOMMUState= *s, } =20 /* Return true if IOVA passes range check, otherwise false. */ -static inline bool vtd_iova_range_check(IntelIOMMUState *s, - uint64_t iova, VTDContextEntry *ce, - uint8_t aw, uint32_t pasid) +static inline bool vtd_iova_sl_range_check(IntelIOMMUState *s, + uint64_t iova, VTDContextEntry = *ce, + uint8_t aw, uint32_t pasid) { /* * Check if @iova is above 2^X-1, where X is the minimum of MGAW @@ -1086,17 +1087,17 @@ static bool vtd_slpte_nonzero_rsvd(uint64_t slpte, = uint32_t level) =20 /* * We should have caught a guest-mis-programmed level earlier, - * via vtd_is_level_supported. + * via vtd_is_sl_level_supported. */ assert(level < VTD_SPTE_RSVD_LEN); /* - * Zero level doesn't exist. The smallest level is VTD_SL_PT_LEVEL=3D1= and - * checked by vtd_is_last_slpte(). + * Zero level doesn't exist. The smallest level is VTD_PT_LEVEL=3D1 and + * checked by vtd_is_last_pte(). */ assert(level); =20 - if ((level =3D=3D VTD_SL_PD_LEVEL || level =3D=3D VTD_SL_PDP_LEVEL) && - (slpte & VTD_SL_PT_PAGE_SIZE_MASK)) { + if ((level =3D=3D VTD_PD_LEVEL || level =3D=3D VTD_PDP_LEVEL) && + (slpte & VTD_PT_PAGE_SIZE_MASK)) { /* large page */ rsvd_mask =3D vtd_spte_rsvd_large[level]; } else { @@ -1122,7 +1123,7 @@ static int vtd_iova_to_slpte(IntelIOMMUState *s, VTDC= ontextEntry *ce, uint64_t access_right_check; uint64_t xlat, size; =20 - if (!vtd_iova_range_check(s, iova, ce, aw_bits, pasid)) { + if (!vtd_iova_sl_range_check(s, iova, ce, aw_bits, pasid)) { error_report_once("%s: detected IOVA overflow (iova=3D0x%" PRIx64 = "," "pasid=3D0x%" PRIx32 ")", __func__, iova, pasid); return -VTD_FR_ADDR_BEYOND_MGAW; @@ -1133,7 +1134,7 @@ static int vtd_iova_to_slpte(IntelIOMMUState *s, VTDC= ontextEntry *ce, =20 while (true) { offset =3D vtd_iova_level_offset(iova, level); - slpte =3D vtd_get_slpte(addr, offset); + slpte =3D vtd_get_pte(addr, offset); =20 if (slpte =3D=3D (uint64_t)-1) { error_report_once("%s: detected read error on DMAR slpte " @@ -1164,17 +1165,17 @@ static int vtd_iova_to_slpte(IntelIOMMUState *s, VT= DContextEntry *ce, return -VTD_FR_PAGING_ENTRY_RSVD; } =20 - if (vtd_is_last_slpte(slpte, level)) { + if (vtd_is_last_pte(slpte, level)) { *slptep =3D slpte; *slpte_level =3D level; break; } - addr =3D vtd_get_slpte_addr(slpte, aw_bits); + addr =3D vtd_get_pte_addr(slpte, aw_bits); level--; } =20 - xlat =3D vtd_get_slpte_addr(*slptep, aw_bits); - size =3D ~vtd_slpt_level_page_mask(level) + 1; + xlat =3D vtd_get_pte_addr(*slptep, aw_bits); + size =3D ~vtd_pt_level_page_mask(level) + 1; =20 /* * From VT-d spec 3.14: Untranslated requests and translation @@ -1325,14 +1326,14 @@ static int vtd_page_walk_level(dma_addr_t addr, uin= t64_t start, =20 trace_vtd_page_walk_level(addr, level, start, end); =20 - subpage_size =3D 1ULL << vtd_slpt_level_shift(level); - subpage_mask =3D vtd_slpt_level_page_mask(level); + subpage_size =3D 1ULL << vtd_pt_level_shift(level); + subpage_mask =3D vtd_pt_level_page_mask(level); =20 while (iova < end) { iova_next =3D (iova & subpage_mask) + subpage_size; =20 offset =3D vtd_iova_level_offset(iova, level); - slpte =3D vtd_get_slpte(addr, offset); + slpte =3D vtd_get_pte(addr, offset); =20 if (slpte =3D=3D (uint64_t)-1) { trace_vtd_page_walk_skip_read(iova, iova_next); @@ -1355,12 +1356,12 @@ static int vtd_page_walk_level(dma_addr_t addr, uin= t64_t start, */ entry_valid =3D read_cur | write_cur; =20 - if (!vtd_is_last_slpte(slpte, level) && entry_valid) { + if (!vtd_is_last_pte(slpte, level) && entry_valid) { /* * This is a valid PDE (or even bigger than PDE). We need * to walk one further level. */ - ret =3D vtd_page_walk_level(vtd_get_slpte_addr(slpte, info->aw= ), + ret =3D vtd_page_walk_level(vtd_get_pte_addr(slpte, info->aw), iova, MIN(iova_next, end), level - 1, read_cur, write_cur, info); } else { @@ -1377,7 +1378,7 @@ static int vtd_page_walk_level(dma_addr_t addr, uint6= 4_t start, event.entry.perm =3D IOMMU_ACCESS_FLAG(read_cur, write_cur); event.entry.addr_mask =3D ~subpage_mask; /* NOTE: this is only meaningful if entry_valid =3D=3D true */ - event.entry.translated_addr =3D vtd_get_slpte_addr(slpte, info= ->aw); + event.entry.translated_addr =3D vtd_get_pte_addr(slpte, info->= aw); event.type =3D event.entry.perm ? IOMMU_NOTIFIER_MAP : IOMMU_NOTIFIER_UNMAP; ret =3D vtd_page_walk_one(&event, info); @@ -1411,11 +1412,11 @@ static int vtd_page_walk(IntelIOMMUState *s, VTDCon= textEntry *ce, dma_addr_t addr =3D vtd_get_iova_pgtbl_base(s, ce, pasid); uint32_t level =3D vtd_get_iova_level(s, ce, pasid); =20 - if (!vtd_iova_range_check(s, start, ce, info->aw, pasid)) { + if (!vtd_iova_sl_range_check(s, start, ce, info->aw, pasid)) { return -VTD_FR_ADDR_BEYOND_MGAW; } =20 - if (!vtd_iova_range_check(s, end, ce, info->aw, pasid)) { + if (!vtd_iova_sl_range_check(s, end, ce, info->aw, pasid)) { /* Fix end so that it reaches the maximum */ end =3D vtd_iova_limit(s, ce, info->aw, pasid); } @@ -1530,7 +1531,7 @@ static int vtd_dev_to_context_entry(IntelIOMMUState *= s, uint8_t bus_num, =20 /* Check if the programming of context-entry is valid */ if (!s->root_scalable && - !vtd_is_level_supported(s, vtd_ce_get_level(ce))) { + !vtd_is_sl_level_supported(s, vtd_ce_get_level(ce))) { error_report_once("%s: invalid context entry: hi=3D%"PRIx64 ", lo=3D%"PRIx64" (level %d not supported)", __func__, ce->hi, ce->lo, @@ -1900,7 +1901,7 @@ static bool vtd_do_iommu_translate(VTDAddressSpace *v= td_as, PCIBus *bus, VTDContextEntry ce; uint8_t bus_num =3D pci_bus_num(bus); VTDContextCacheEntry *cc_entry; - uint64_t slpte, page_mask; + uint64_t pte, page_mask; uint32_t level, pasid =3D vtd_as->pasid; uint16_t source_id =3D PCI_BUILD_BDF(bus_num, devfn); int ret_fr; @@ -1921,13 +1922,13 @@ static bool vtd_do_iommu_translate(VTDAddressSpace = *vtd_as, PCIBus *bus, =20 cc_entry =3D &vtd_as->context_cache_entry; =20 - /* Try to fetch slpte form IOTLB, we don't need RID2PASID logic */ + /* Try to fetch pte form IOTLB, we don't need RID2PASID logic */ if (!rid2pasid) { iotlb_entry =3D vtd_lookup_iotlb(s, source_id, pasid, addr); if (iotlb_entry) { - trace_vtd_iotlb_page_hit(source_id, addr, iotlb_entry->slpte, + trace_vtd_iotlb_page_hit(source_id, addr, iotlb_entry->pte, iotlb_entry->domain_id); - slpte =3D iotlb_entry->slpte; + pte =3D iotlb_entry->pte; access_flags =3D iotlb_entry->access_flags; page_mask =3D iotlb_entry->mask; goto out; @@ -1999,20 +2000,20 @@ static bool vtd_do_iommu_translate(VTDAddressSpace = *vtd_as, PCIBus *bus, return true; } =20 - /* Try to fetch slpte form IOTLB for RID2PASID slow path */ + /* Try to fetch pte form IOTLB for RID2PASID slow path */ if (rid2pasid) { iotlb_entry =3D vtd_lookup_iotlb(s, source_id, pasid, addr); if (iotlb_entry) { - trace_vtd_iotlb_page_hit(source_id, addr, iotlb_entry->slpte, + trace_vtd_iotlb_page_hit(source_id, addr, iotlb_entry->pte, iotlb_entry->domain_id); - slpte =3D iotlb_entry->slpte; + pte =3D iotlb_entry->pte; access_flags =3D iotlb_entry->access_flags; page_mask =3D iotlb_entry->mask; goto out; } } =20 - ret_fr =3D vtd_iova_to_slpte(s, &ce, addr, is_write, &slpte, &level, + ret_fr =3D vtd_iova_to_slpte(s, &ce, addr, is_write, &pte, &level, &reads, &writes, s->aw_bits, pasid); if (ret_fr) { vtd_report_fault(s, -ret_fr, is_fpd_set, source_id, @@ -2020,14 +2021,14 @@ static bool vtd_do_iommu_translate(VTDAddressSpace = *vtd_as, PCIBus *bus, goto error; } =20 - page_mask =3D vtd_slpt_level_page_mask(level); + page_mask =3D vtd_pt_level_page_mask(level); access_flags =3D IOMMU_ACCESS_FLAG(reads, writes); vtd_update_iotlb(s, source_id, vtd_get_domain_id(s, &ce, pasid), - addr, slpte, access_flags, level, pasid); + addr, pte, access_flags, level, pasid); out: vtd_iommu_unlock(s); entry->iova =3D addr & page_mask; - entry->translated_addr =3D vtd_get_slpte_addr(slpte, s->aw_bits) & pag= e_mask; + entry->translated_addr =3D vtd_get_pte_addr(pte, s->aw_bits) & page_ma= sk; entry->addr_mask =3D ~page_mask; entry->perm =3D access_flags; return true; --=20 2.34.1 From nobody Mon Sep 16 19:12:33 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1721290922; cv=none; d=zohomail.com; s=zohoarc; b=DJnn0MYzhYQUq41WwnWxFbEnBSAZbcqhLS3+E0HigXFYjwkHzdYXsDLUOH40SfYAUYXlb0SqnOLp7B9VIJ5VRswdFxxm6Kcis7wlVO8mi9gUQDbXqE6CG8Y8WUBqbbnI9YhzVQc5zRYEHuo24xCXC/9vi3Mfx0/5AbUUNK5bqr4= ARC-Message-Signature: i=1; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.13; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1721290923430116600 From: Yi Liu This adds stage-1 page table walking to support stage-1 only transltion in scalable modern mode. Signed-off-by: Yi Liu Co-developed-by: Cl=C3=A9ment Mathieu--Drif Signed-off-by: Cl=C3=A9ment Mathieu--Drif Signed-off-by: Yi Sun Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu_internal.h | 26 ++++++ hw/i386/intel_iommu.c | 146 ++++++++++++++++++++++++++++++++- 2 files changed, 168 insertions(+), 4 deletions(-) diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h index 1875c2ddd6..36fcc6bb5e 100644 --- a/hw/i386/intel_iommu_internal.h +++ b/hw/i386/intel_iommu_internal.h @@ -440,6 +440,24 @@ typedef union VTDInvDesc VTDInvDesc; (0x3ffff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM | VTD_SL_TM))= : \ (0x3ffff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM)) =20 +/* Rsvd field masks for fpte */ +#define VTD_FS_UPPER_IGNORED 0xfff0000000000000ULL +#define VTD_FPTE_PAGE_L1_RSVD_MASK(aw) (~(VTD_HAW_MASK(aw)) & \ + (~VTD_FS_UPPER_IGNORED)) +#define VTD_FPTE_PAGE_L2_RSVD_MASK(aw) (~(VTD_HAW_MASK(aw)) & \ + (~VTD_FS_UPPER_IGNORED)) +#define VTD_FPTE_PAGE_L3_RSVD_MASK(aw) (~(VTD_HAW_MASK(aw)) & \ + (~VTD_FS_UPPER_IGNORED)) +#define VTD_FPTE_PAGE_L3_FS1GP_RSVD_MASK(aw) ((0x3fffe000ULL | \ + ~(VTD_HAW_MASK(aw))) \ + & (~VTD_FS_UPPER_IGNORED)) +#define VTD_FPTE_PAGE_L2_FS2MP_RSVD_MASK(aw) ((0x1fe000ULL | \ + ~(VTD_HAW_MASK(aw))) \ + & (~VTD_FS_UPPER_IGNORED)) +#define VTD_FPTE_PAGE_L4_RSVD_MASK(aw) ((0x80ULL | \ + ~(VTD_HAW_MASK(aw))) \ + & (~VTD_FS_UPPER_IGNORED)) + #define VTD_INV_DESC_PIOTLB_ALL_IN_PASID (2ULL << 4) #define VTD_INV_DESC_PIOTLB_PSI_IN_PASID (3ULL << 4) =20 @@ -533,6 +551,14 @@ typedef struct VTDRootEntry VTDRootEntry; #define VTD_SM_PASID_ENTRY_AW 7ULL /* Adjusted guest-address-widt= h */ #define VTD_SM_PASID_ENTRY_DID(val) ((val) & VTD_DOMAIN_ID_MASK) =20 +#define VTD_SM_PASID_ENTRY_FLPM 3ULL +#define VTD_SM_PASID_ENTRY_FLPTPTR (~0xfffULL) + +/* First Level Paging Structure */ +/* Masks for First Level Paging Entry */ +#define VTD_FL_P 1ULL +#define VTD_FL_RW_MASK (1ULL << 1) + /* Second Level Page Translation Pointer*/ #define VTD_SM_PASID_ENTRY_SLPTPTR (~0xfffULL) =20 diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 94f6532935..287741b687 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -48,6 +48,8 @@ =20 /* pe operations */ #define VTD_PE_GET_TYPE(pe) ((pe)->val[0] & VTD_SM_PASID_ENTRY_PGTT) +#define VTD_PE_GET_FL_LEVEL(pe) \ + (4 + (((pe)->val[2] >> 2) & VTD_SM_PASID_ENTRY_FLPM)) #define VTD_PE_GET_SL_LEVEL(pe) \ (2 + (((pe)->val[0] >> 2) & VTD_SM_PASID_ENTRY_AW)) =20 @@ -755,6 +757,11 @@ static inline bool vtd_is_sl_level_supported(IntelIOMM= UState *s, uint32_t level) (1ULL << (level - 2 + VTD_CAP_SAGAW_SHIFT)); } =20 +static inline bool vtd_is_fl_level_supported(IntelIOMMUState *s, uint32_t = level) +{ + return level =3D=3D VTD_PML4_LEVEL; +} + /* Return true if check passed, otherwise false */ static inline bool vtd_pe_type_check(IntelIOMMUState *s, VTDPASIDEntry *pe) { @@ -841,6 +848,11 @@ static int vtd_get_pe_in_pasid_leaf_table(IntelIOMMUSt= ate *s, return -VTD_FR_PASID_TABLE_ENTRY_INV; } =20 + if (pgtt =3D=3D VTD_SM_PASID_ENTRY_FLT && + !vtd_is_fl_level_supported(s, VTD_PE_GET_FL_LEVEL(pe))) { + return -VTD_FR_PASID_TABLE_ENTRY_INV; + } + return 0; } =20 @@ -976,7 +988,11 @@ static uint32_t vtd_get_iova_level(IntelIOMMUState *s, =20 if (s->root_scalable) { vtd_ce_get_rid2pasid_entry(s, ce, &pe, pasid); - return VTD_PE_GET_SL_LEVEL(&pe); + if (s->scalable_modern) { + return VTD_PE_GET_FL_LEVEL(&pe); + } else { + return VTD_PE_GET_SL_LEVEL(&pe); + } } =20 return vtd_ce_get_level(ce); @@ -1063,7 +1079,11 @@ static dma_addr_t vtd_get_iova_pgtbl_base(IntelIOMMU= State *s, =20 if (s->root_scalable) { vtd_ce_get_rid2pasid_entry(s, ce, &pe, pasid); - return pe.val[0] & VTD_SM_PASID_ENTRY_SLPTPTR; + if (s->scalable_modern) { + return pe.val[2] & VTD_SM_PASID_ENTRY_FLPTPTR; + } else { + return pe.val[0] & VTD_SM_PASID_ENTRY_SLPTPTR; + } } =20 return vtd_ce_get_slpt_base(ce); @@ -1865,6 +1885,104 @@ out: trace_vtd_pt_enable_fast_path(source_id, success); } =20 +/* + * Rsvd field masks for fpte: + * vtd_fpte_rsvd 4k pages + * vtd_fpte_rsvd_large large pages + * + * We support only 4-level page tables. + */ +#define VTD_FPTE_RSVD_LEN 5 +static uint64_t vtd_fpte_rsvd[VTD_FPTE_RSVD_LEN]; +static uint64_t vtd_fpte_rsvd_large[VTD_FPTE_RSVD_LEN]; + +static bool vtd_flpte_nonzero_rsvd(uint64_t flpte, uint32_t level) +{ + uint64_t rsvd_mask; + + /* + * We should have caught a guest-mis-programmed level earlier, + * via vtd_is_fl_level_supported. + */ + assert(level < VTD_SPTE_RSVD_LEN); + /* + * Zero level doesn't exist. The smallest level is VTD_PT_LEVEL=3D1 and + * checked by vtd_is_last_pte(). + */ + assert(level); + + if ((level =3D=3D VTD_PD_LEVEL || level =3D=3D VTD_PDP_LEVEL) && + (flpte & VTD_PT_PAGE_SIZE_MASK)) { + /* large page */ + rsvd_mask =3D vtd_fpte_rsvd_large[level]; + } else { + rsvd_mask =3D vtd_fpte_rsvd[level]; + } + + return flpte & rsvd_mask; +} + +static inline bool vtd_flpte_present(uint64_t flpte) +{ + return !!(flpte & VTD_FL_P); +} + +/* + * Given the @iova, get relevant @flptep. @flpte_level will be the last le= vel + * of the translation, can be used for deciding the size of large page. + */ +static int vtd_iova_to_flpte(IntelIOMMUState *s, VTDContextEntry *ce, + uint64_t iova, bool is_write, + uint64_t *flptep, uint32_t *flpte_level, + bool *reads, bool *writes, uint8_t aw_bits, + uint32_t pasid) +{ + dma_addr_t addr =3D vtd_get_iova_pgtbl_base(s, ce, pasid); + uint32_t level =3D vtd_get_iova_level(s, ce, pasid); + uint32_t offset; + uint64_t flpte; + + while (true) { + offset =3D vtd_iova_level_offset(iova, level); + flpte =3D vtd_get_pte(addr, offset); + + if (flpte =3D=3D (uint64_t)-1) { + if (level =3D=3D vtd_get_iova_level(s, ce, pasid)) { + /* Invalid programming of context-entry */ + return -VTD_FR_CONTEXT_ENTRY_INV; + } else { + return -VTD_FR_PAGING_ENTRY_INV; + } + } + if (!vtd_flpte_present(flpte)) { + *reads =3D false; + *writes =3D false; + return -VTD_FR_PAGING_ENTRY_INV; + } + *reads =3D true; + *writes =3D (*writes) && (flpte & VTD_FL_RW_MASK); + if (is_write && !(flpte & VTD_FL_RW_MASK)) { + return -VTD_FR_WRITE; + } + if (vtd_flpte_nonzero_rsvd(flpte, level)) { + error_report_once("%s: detected flpte reserved non-zero " + "iova=3D0x%" PRIx64 ", level=3D0x%" PRIx32 + "flpte=3D0x%" PRIx64 ", pasid=3D0x%" PRIX32 = ")", + __func__, iova, level, flpte, pasid); + return -VTD_FR_PAGING_ENTRY_RSVD; + } + + if (vtd_is_last_pte(flpte, level)) { + *flptep =3D flpte; + *flpte_level =3D level; + return 0; + } + + addr =3D vtd_get_pte_addr(flpte, aw_bits); + level--; + } +} + static void vtd_report_fault(IntelIOMMUState *s, int err, bool is_fpd_set, uint16_t source_id, @@ -2013,8 +2131,13 @@ static bool vtd_do_iommu_translate(VTDAddressSpace *= vtd_as, PCIBus *bus, } } =20 - ret_fr =3D vtd_iova_to_slpte(s, &ce, addr, is_write, &pte, &level, - &reads, &writes, s->aw_bits, pasid); + if (s->scalable_modern && s->root_scalable) { + ret_fr =3D vtd_iova_to_flpte(s, &ce, addr, is_write, &pte, &level, + &reads, &writes, s->aw_bits, pasid); + } else { + ret_fr =3D vtd_iova_to_slpte(s, &ce, addr, is_write, &pte, &level, + &reads, &writes, s->aw_bits, pasid); + } if (ret_fr) { vtd_report_fault(s, -ret_fr, is_fpd_set, source_id, addr, is_write, pasid !=3D PCI_NO_PASID, pasid); @@ -4231,6 +4354,21 @@ static void vtd_init(IntelIOMMUState *s) vtd_spte_rsvd_large[3] =3D VTD_SPTE_LPAGE_L3_RSVD_MASK(s->aw_bits, x86_iommu->dt_supporte= d); =20 + /* + * Rsvd field masks for fpte + */ + vtd_fpte_rsvd[0] =3D ~0ULL; + vtd_fpte_rsvd[1] =3D VTD_FPTE_PAGE_L1_RSVD_MASK(s->aw_bits); + vtd_fpte_rsvd[2] =3D VTD_FPTE_PAGE_L2_RSVD_MASK(s->aw_bits); + vtd_fpte_rsvd[3] =3D VTD_FPTE_PAGE_L3_RSVD_MASK(s->aw_bits); + vtd_fpte_rsvd[4] =3D VTD_FPTE_PAGE_L4_RSVD_MASK(s->aw_bits); + + vtd_fpte_rsvd_large[0] =3D ~0ULL; + vtd_fpte_rsvd_large[1] =3D ~0ULL; + vtd_fpte_rsvd_large[2] =3D VTD_FPTE_PAGE_L2_FS2MP_RSVD_MASK(s->aw_bits= ); + vtd_fpte_rsvd_large[3] =3D VTD_FPTE_PAGE_L3_FS1GP_RSVD_MASK(s->aw_bits= ); + vtd_fpte_rsvd_large[4] =3D ~0ULL; + if (s->scalable_mode || s->snoop_control) { vtd_spte_rsvd[1] &=3D ~VTD_SPTE_SNP; vtd_spte_rsvd_large[2] &=3D ~VTD_SPTE_SNP; --=20 2.34.1 From nobody Mon Sep 16 19:12:33 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1721290910; cv=none; d=zohomail.com; s=zohoarc; b=k4pqB5Rp7rVJcTo0EQCX5zrx1XNXsP+Ctd+l9tAYL6moVxwYNqrjvNz1tn9VtsD6F51MbEn9i8vqjDsiRWNqMn4AkJGMVj9Xyxi4YeK06PbGtUGO17ng1UM9bQj+8BxFOds9yBK22AGqCBRKkZar8tPCyvs14XcA7Nex6zOjSoI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1721290910; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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X-CSE-ConnectionGUID: +azIJVQqSuqN7wb0uGarog== X-CSE-MsgGUID: T6sDwFv8SWG87Cstz0Wj8Q== X-IronPort-AV: E=McAfee;i="6700,10204,11136"; a="29996221" X-IronPort-AV: E=Sophos;i="6.09,217,1716274800"; d="scan'208";a="29996221" X-CSE-ConnectionGUID: P+wvWxUqTQKupKtFMgw8lA== X-CSE-MsgGUID: EfmSh1c1Qnyo/qLLYWWShQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,217,1716274800"; d="scan'208";a="81717265" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, peterx@redhat.com, jasowang@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Zhenzhong Duan , Marcel Apfelbaum , Paolo Bonzini , Richard Henderson , Eduardo Habkost Subject: [PATCH v1 07/17] intel_iommu: Check if the input address is canonical Date: Thu, 18 Jul 2024 16:16:26 +0800 Message-Id: <20240718081636.879544-8-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240718081636.879544-1-zhenzhong.duan@intel.com> References: <20240718081636.879544-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.13; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1721290911262116600 From: Cl=C3=A9ment Mathieu--Drif First stage translation must fail if the address to translate is not canonical. Signed-off-by: Cl=C3=A9ment Mathieu--Drif Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu_internal.h | 2 ++ hw/i386/intel_iommu.c | 21 +++++++++++++++++++++ 2 files changed, 23 insertions(+) diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h index 36fcc6bb5e..168185b850 100644 --- a/hw/i386/intel_iommu_internal.h +++ b/hw/i386/intel_iommu_internal.h @@ -322,6 +322,8 @@ typedef enum VTDFaultReason { VTD_FR_PASID_ENTRY_P =3D 0x59, VTD_FR_PASID_TABLE_ENTRY_INV =3D 0x5b, /*Invalid PASID table entry */ =20 + VTD_FR_FS_NON_CANONICAL =3D 0x80, /* SNG.1 : Address for FS not canoni= cal.*/ + /* Output address in the interrupt address range for scalable mode */ VTD_FR_SM_INTERRUPT_ADDR =3D 0x87, VTD_FR_MAX, /* Guard */ diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 287741b687..495a41cf80 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -1824,6 +1824,7 @@ static const bool vtd_qualified_faults[] =3D { [VTD_FR_PASID_ENTRY_P] =3D true, [VTD_FR_PASID_TABLE_ENTRY_INV] =3D true, [VTD_FR_SM_INTERRUPT_ADDR] =3D true, + [VTD_FR_FS_NON_CANONICAL] =3D true, [VTD_FR_MAX] =3D false, }; =20 @@ -1927,6 +1928,20 @@ static inline bool vtd_flpte_present(uint64_t flpte) return !!(flpte & VTD_FL_P); } =20 +/* Return true if IOVA is canonical, otherwise false. */ +static bool vtd_iova_fl_check_canonical(IntelIOMMUState *s, uint64_t iova, + VTDContextEntry *ce, uint32_t pasi= d) +{ + uint64_t iova_limit =3D vtd_iova_limit(s, ce, s->aw_bits, pasid); + uint64_t upper_bits_mask =3D ~(iova_limit - 1); + uint64_t upper_bits =3D iova & upper_bits_mask; + bool msb =3D ((iova & (iova_limit >> 1)) !=3D 0); + return !( + (!msb && (upper_bits !=3D 0)) || + (msb && (upper_bits !=3D upper_bits_mask)) + ); +} + /* * Given the @iova, get relevant @flptep. @flpte_level will be the last le= vel * of the translation, can be used for deciding the size of large page. @@ -1942,6 +1957,12 @@ static int vtd_iova_to_flpte(IntelIOMMUState *s, VTD= ContextEntry *ce, uint32_t offset; uint64_t flpte; =20 + if (!vtd_iova_fl_check_canonical(s, iova, ce, pasid)) { + error_report_once("%s: detected non canonical IOVA (iova=3D0x%" PR= Ix64 "," + "pasid=3D0x%" PRIx32 ")", __func__, iova, pasid); + return -VTD_FR_FS_NON_CANONICAL; + } + while (true) { offset =3D vtd_iova_level_offset(iova, level); flpte =3D vtd_get_pte(addr, offset); --=20 2.34.1 From nobody Mon Sep 16 19:12:33 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1721290938; cv=none; d=zohomail.com; s=zohoarc; b=SpMnkP8osNdXuajfRdMs/9LK1mpUPdhw6B/DCTnVz1tpwNNpiwIU2IO2h5yawEQk6X1lHP6+JfT8Xl9xFiDUA7js2l2CfM7q7BbAeKHRafhdPhMLAfb2JEWV81ecdvqhBowTK+7uisXFjNDLqhgsA/cDuKaXwIbrOV0f53p1eDA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1721290938; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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X-CSE-ConnectionGUID: HkibuFL0SUO815dmzIKDJw== X-CSE-MsgGUID: 62NhtFBXSSmTTnzHBW/WfA== X-IronPort-AV: E=McAfee;i="6700,10204,11136"; a="29996259" X-IronPort-AV: E=Sophos;i="6.09,217,1716274800"; d="scan'208";a="29996259" X-CSE-ConnectionGUID: 7QUNIG2HQ7K+eWSKnl6QkQ== X-CSE-MsgGUID: ZeQkuc2aQimmTqP3g/ydzQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,217,1716274800"; d="scan'208";a="81717300" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, peterx@redhat.com, jasowang@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Zhenzhong Duan , Paolo Bonzini , Richard Henderson , Eduardo Habkost , Marcel Apfelbaum Subject: [PATCH v1 08/17] intel_iommu: Set accessed and dirty bits during first stage translation Date: Thu, 18 Jul 2024 16:16:27 +0800 Message-Id: <20240718081636.879544-9-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240718081636.879544-1-zhenzhong.duan@intel.com> References: <20240718081636.879544-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.13; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1721290939462116600 From: Cl=C3=A9ment Mathieu--Drif Signed-off-by: Cl=C3=A9ment Mathieu--Drif Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu_internal.h | 3 +++ hw/i386/intel_iommu.c | 24 ++++++++++++++++++++++++ 2 files changed, 27 insertions(+) diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h index 168185b850..cf0f176e06 100644 --- a/hw/i386/intel_iommu_internal.h +++ b/hw/i386/intel_iommu_internal.h @@ -326,6 +326,7 @@ typedef enum VTDFaultReason { =20 /* Output address in the interrupt address range for scalable mode */ VTD_FR_SM_INTERRUPT_ADDR =3D 0x87, + VTD_FR_FS_BIT_UPDATE_FAILED =3D 0x91, /* SFS.10 */ VTD_FR_MAX, /* Guard */ } VTDFaultReason; =20 @@ -560,6 +561,8 @@ typedef struct VTDRootEntry VTDRootEntry; /* Masks for First Level Paging Entry */ #define VTD_FL_P 1ULL #define VTD_FL_RW_MASK (1ULL << 1) +#define VTD_FL_A 0x20 +#define VTD_FL_D 0x40 =20 /* Second Level Page Translation Pointer*/ #define VTD_SM_PASID_ENTRY_SLPTPTR (~0xfffULL) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 495a41cf80..210df32f01 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -1825,6 +1825,7 @@ static const bool vtd_qualified_faults[] =3D { [VTD_FR_PASID_TABLE_ENTRY_INV] =3D true, [VTD_FR_SM_INTERRUPT_ADDR] =3D true, [VTD_FR_FS_NON_CANONICAL] =3D true, + [VTD_FR_FS_BIT_UPDATE_FAILED] =3D true, [VTD_FR_MAX] =3D false, }; =20 @@ -1942,6 +1943,20 @@ static bool vtd_iova_fl_check_canonical(IntelIOMMUSt= ate *s, uint64_t iova, ); } =20 +static MemTxResult vtd_set_flag_in_pte(dma_addr_t base_addr, uint32_t inde= x, + uint64_t pte, uint64_t flag) +{ + if (pte & flag) { + return MEMTX_OK; + } + pte |=3D flag; + pte =3D cpu_to_le64(pte); + return dma_memory_write(&address_space_memory, + base_addr + index * sizeof(pte), + &pte, sizeof(pte), + MEMTXATTRS_UNSPECIFIED); +} + /* * Given the @iova, get relevant @flptep. @flpte_level will be the last le= vel * of the translation, can be used for deciding the size of large page. @@ -1993,7 +2008,16 @@ static int vtd_iova_to_flpte(IntelIOMMUState *s, VTD= ContextEntry *ce, return -VTD_FR_PAGING_ENTRY_RSVD; } =20 + if (vtd_set_flag_in_pte(addr, offset, flpte, VTD_FL_A) !=3D MEMTX_= OK) { + return -VTD_FR_FS_BIT_UPDATE_FAILED; + } + if (vtd_is_last_pte(flpte, level)) { + if (is_write && + (vtd_set_flag_in_pte(addr, offset, flpte, VTD_FL_D) !=3D + MEMTX_= OK)) { + return -VTD_FR_FS_BIT_UPDATE_FAILED; + } *flptep =3D flpte; *flpte_level =3D level; return 0; --=20 2.34.1 From nobody Mon Sep 16 19:12:33 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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d="scan'208";a="81717357" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, peterx@redhat.com, jasowang@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Zhenzhong Duan , Paolo Bonzini , Richard Henderson , Eduardo Habkost , Marcel Apfelbaum Subject: [PATCH v1 09/17] intel_iommu: Flush stage-1 cache in iotlb invalidation Date: Thu, 18 Jul 2024 16:16:28 +0800 Message-Id: <20240718081636.879544-10-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240718081636.879544-1-zhenzhong.duan@intel.com> References: <20240718081636.879544-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.13; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1721290903317116600 Content-Type: text/plain; charset="utf-8" According to spec, Page-Selective-within-Domain Invalidation (11b): 1. IOTLB entries caching second-stage mappings (PGTT=3D010b) or pass-through (PGTT=3D100b) mappings associated with the specified domain-id and the input-address range are invalidated. 2. IOTLB entries caching first-stage (PGTT=3D001b) or nested (PGTT=3D011b) mapping associated with specified domain-id are invalidated. So per spec definition the Page-Selective-within-Domain Invalidation needs to flush first stage and nested cached IOTLB enties as well. We don't support nested yet and pass-through mapping is never cached, so what in iotlb cache are only first-stage and second-stage mappings. Add a tag pgtt in VTDIOTLBEntry to mark PGTT type of the mapping and invalidate entries based on PGTT type. Signed-off-by: Zhenzhong Duan --- include/hw/i386/intel_iommu.h | 1 + hw/i386/intel_iommu.c | 27 +++++++++++++++++++++------ 2 files changed, 22 insertions(+), 6 deletions(-) diff --git a/include/hw/i386/intel_iommu.h b/include/hw/i386/intel_iommu.h index fe9057c50d..b843d069cc 100644 --- a/include/hw/i386/intel_iommu.h +++ b/include/hw/i386/intel_iommu.h @@ -155,6 +155,7 @@ struct VTDIOTLBEntry { uint64_t pte; uint64_t mask; uint8_t access_flags; + uint8_t pgtt; }; =20 /* VT-d Source-ID Qualifier types */ diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 210df32f01..8d47e5ba78 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -305,9 +305,21 @@ static gboolean vtd_hash_remove_by_page(gpointer key, = gpointer value, VTDIOTLBPageInvInfo *info =3D (VTDIOTLBPageInvInfo *)user_data; uint64_t gfn =3D (info->addr >> VTD_PAGE_SHIFT_4K) & info->mask; uint64_t gfn_tlb =3D (info->addr & entry->mask) >> VTD_PAGE_SHIFT_4K; - return (entry->domain_id =3D=3D info->domain_id) && - (((entry->gfn & info->mask) =3D=3D gfn) || - (entry->gfn =3D=3D gfn_tlb)); + + if (entry->domain_id !=3D info->domain_id) { + return false; + } + + /* + * According to spec, IOTLB entries caching first-stage (PGTT=3D001b) = or + * nested (PGTT=3D011b) mapping associated with specified domain-id are + * invalidated. Nested isn't supported yet, so only need to check 001b. + */ + if (entry->pgtt =3D=3D VTD_SM_PASID_ENTRY_FLT) { + return true; + } + + return (entry->gfn & info->mask) =3D=3D gfn || entry->gfn =3D=3D gfn_t= lb; } =20 /* Reset all the gen of VTDAddressSpace to zero and set the gen of @@ -382,7 +394,7 @@ out: static void vtd_update_iotlb(IntelIOMMUState *s, uint16_t source_id, uint16_t domain_id, hwaddr addr, uint64_t pte, uint8_t access_flags, uint32_t level, - uint32_t pasid) + uint32_t pasid, uint8_t pgtt) { VTDIOTLBEntry *entry =3D g_malloc(sizeof(*entry)); struct vtd_iotlb_key *key =3D g_malloc(sizeof(*key)); @@ -400,6 +412,7 @@ static void vtd_update_iotlb(IntelIOMMUState *s, uint16= _t source_id, entry->access_flags =3D access_flags; entry->mask =3D vtd_pt_level_page_mask(level); entry->pasid =3D pasid; + entry->pgtt =3D pgtt; =20 key->gfn =3D gfn; key->sid =3D source_id; @@ -2071,7 +2084,7 @@ static bool vtd_do_iommu_translate(VTDAddressSpace *v= td_as, PCIBus *bus, bool is_fpd_set =3D false; bool reads =3D true; bool writes =3D true; - uint8_t access_flags; + uint8_t access_flags, pgtt; bool rid2pasid =3D (pasid =3D=3D PCI_NO_PASID) && s->root_scalable; VTDIOTLBEntry *iotlb_entry; =20 @@ -2179,9 +2192,11 @@ static bool vtd_do_iommu_translate(VTDAddressSpace *= vtd_as, PCIBus *bus, if (s->scalable_modern && s->root_scalable) { ret_fr =3D vtd_iova_to_flpte(s, &ce, addr, is_write, &pte, &level, &reads, &writes, s->aw_bits, pasid); + pgtt =3D VTD_SM_PASID_ENTRY_FLT; } else { ret_fr =3D vtd_iova_to_slpte(s, &ce, addr, is_write, &pte, &level, &reads, &writes, s->aw_bits, pasid); + pgtt =3D VTD_SM_PASID_ENTRY_SLT; } if (ret_fr) { vtd_report_fault(s, -ret_fr, is_fpd_set, source_id, @@ -2192,7 +2207,7 @@ static bool vtd_do_iommu_translate(VTDAddressSpace *v= td_as, PCIBus *bus, page_mask =3D vtd_pt_level_page_mask(level); access_flags =3D IOMMU_ACCESS_FLAG(reads, writes); vtd_update_iotlb(s, source_id, vtd_get_domain_id(s, &ce, pasid), - addr, pte, access_flags, level, pasid); + addr, pte, access_flags, level, pasid, pgtt); out: vtd_iommu_unlock(s); entry->iova =3D addr & page_mask; --=20 2.34.1 From nobody Mon Sep 16 19:12:33 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1721290915; cv=none; d=zohomail.com; s=zohoarc; b=kvwX15mzcRSIoh/6Kd4dOo22yot+MSKMPsraqFU9Psdjrid5YBlKWFYQTQiAInFJ8QPDSrtKiaqnNe45FSjXX1ixIyZB5ZKDph1LZDNLegjKYgSUaPsH/lLkitnqx8kuds9nT4nlIg+vMQCM1QKaUlHnVZihT17oy+EM872vb7E= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1721290915; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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X-CSE-ConnectionGUID: a3R9e3JFSkKZfogsugCzaQ== X-CSE-MsgGUID: k+/fr3C9RSaQw3vMjt4Ceg== X-IronPort-AV: E=McAfee;i="6700,10204,11136"; a="29996327" X-IronPort-AV: E=Sophos;i="6.09,217,1716274800"; d="scan'208";a="29996327" X-CSE-ConnectionGUID: jOjSYIZISeCLxsw/gnX75Q== X-CSE-MsgGUID: HznIbPiERVmGfm/JTE1DoA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,217,1716274800"; d="scan'208";a="81717400" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, peterx@redhat.com, jasowang@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Zhenzhong Duan , Marcel Apfelbaum , Paolo Bonzini , Richard Henderson , Eduardo Habkost Subject: [PATCH v1 10/17] intel_iommu: Process PASID-based iotlb invalidation Date: Thu, 18 Jul 2024 16:16:29 +0800 Message-Id: <20240718081636.879544-11-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240718081636.879544-1-zhenzhong.duan@intel.com> References: <20240718081636.879544-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.13; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1721290917296116600 Content-Type: text/plain; charset="utf-8" PASID-based iotlb (piotlb) is used during walking Intel VT-d stage-1 page table. This emulates the stage-1 page table iotlb invalidation requested by a PASID-based IOTLB Invalidate Descriptor (P_IOTLB). Signed-off-by: Yi Liu Signed-off-by: Zhenzhong Duan Reviewed-by: Cl=C3=A9ment Mathieu--Drif --- hw/i386/intel_iommu_internal.h | 3 +++ hw/i386/intel_iommu.c | 45 ++++++++++++++++++++++++++++++++++ 2 files changed, 48 insertions(+) diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h index cf0f176e06..7dd8176e86 100644 --- a/hw/i386/intel_iommu_internal.h +++ b/hw/i386/intel_iommu_internal.h @@ -470,6 +470,9 @@ typedef union VTDInvDesc VTDInvDesc; #define VTD_INV_DESC_PIOTLB_PASID(val) (((val) >> 32) & 0xfffffULL) #define VTD_INV_DESC_PIOTLB_DID(val) (((val) >> 16) & \ VTD_DOMAIN_ID_MASK) +#define VTD_INV_DESC_PIOTLB_ADDR(val) ((val) & ~0xfffULL) +#define VTD_INV_DESC_PIOTLB_AM(val) ((val) & 0x3fULL) +#define VTD_INV_DESC_PIOTLB_IH(val) (((val) >> 6) & 0x1) =20 /* Information about page-selective IOTLB invalidate */ struct VTDIOTLBPageInvInfo { diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 8d47e5ba78..8ebb6dbd7d 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -322,6 +322,28 @@ static gboolean vtd_hash_remove_by_page(gpointer key, = gpointer value, return (entry->gfn & info->mask) =3D=3D gfn || entry->gfn =3D=3D gfn_t= lb; } =20 +static gboolean vtd_hash_remove_by_page_piotlb(gpointer key, gpointer valu= e, + gpointer user_data) +{ + VTDIOTLBEntry *entry =3D (VTDIOTLBEntry *)value; + VTDIOTLBPageInvInfo *info =3D (VTDIOTLBPageInvInfo *)user_data; + uint64_t gfn =3D (info->addr >> VTD_PAGE_SHIFT_4K) & info->mask; + uint64_t gfn_tlb =3D (info->addr & entry->mask) >> VTD_PAGE_SHIFT_4K; + + /* + * According to spec, PASID-based-IOTLB Invalidation in page granulari= ty + * doesn't invalidate IOTLB entries caching second-stage (PGTT=3D010b) + * or pass-through (PGTT=3D100b) mappings. Nested isn't supported yet, + * so only need to check first-stage (PGTT=3D001b) mappings. + */ + if (entry->pgtt !=3D VTD_SM_PASID_ENTRY_FLT) { + return false; + } + + return entry->domain_id =3D=3D info->domain_id && entry->pasid =3D=3D = info->pasid && + ((entry->gfn & info->mask) =3D=3D gfn || entry->gfn =3D=3D gfn_= tlb); +} + /* Reset all the gen of VTDAddressSpace to zero and set the gen of * IntelIOMMUState to 1. Must be called with IOMMU lock held. */ @@ -2886,11 +2908,30 @@ static void vtd_piotlb_pasid_invalidate(IntelIOMMUS= tate *s, } } =20 +static void vtd_piotlb_page_invalidate(IntelIOMMUState *s, uint16_t domain= _id, + uint32_t pasid, hwaddr addr, uint8_= t am, + bool ih) +{ + VTDIOTLBPageInvInfo info; + + info.domain_id =3D domain_id; + info.pasid =3D pasid; + info.addr =3D addr; + info.mask =3D ~((1 << am) - 1); + + vtd_iommu_lock(s); + g_hash_table_foreach_remove(s->iotlb, + vtd_hash_remove_by_page_piotlb, &info); + vtd_iommu_unlock(s); +} + static bool vtd_process_piotlb_desc(IntelIOMMUState *s, VTDInvDesc *inv_desc) { uint16_t domain_id; uint32_t pasid; + uint8_t am; + hwaddr addr; =20 if ((inv_desc->val[0] & VTD_INV_DESC_PIOTLB_RSVD_VAL0) || (inv_desc->val[1] & VTD_INV_DESC_PIOTLB_RSVD_VAL1)) { @@ -2907,6 +2948,10 @@ static bool vtd_process_piotlb_desc(IntelIOMMUState = *s, break; =20 case VTD_INV_DESC_PIOTLB_PSI_IN_PASID: + am =3D VTD_INV_DESC_PIOTLB_AM(inv_desc->val[1]); + addr =3D (hwaddr) VTD_INV_DESC_PIOTLB_ADDR(inv_desc->val[1]); + vtd_piotlb_page_invalidate(s, domain_id, pasid, addr, am, + VTD_INV_DESC_PIOTLB_IH(inv_desc->val[1]= )); break; =20 default: --=20 2.34.1 From nobody Mon Sep 16 19:12:33 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1721290880; cv=none; d=zohomail.com; s=zohoarc; b=LPJ2Blsb+7YmxOQ/ksKgbm2ob+Unt0NscT1aWNhbPsjLi7vH+UeEeIcy45LeLB3eLOhtI2+VJA/t8DqFfbMzRscZI6iv4xdpxNlfwG5RJ+6EkZudhrYRTRoM5igEkQt6k9p9a8yXa8B9DRyYVHPwh2rCE8IhdC6BGXDUHVd5eQA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1721290880; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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X-CSE-ConnectionGUID: KPbFQV/VTmeooYZc33YISg== X-CSE-MsgGUID: vDIVXzi0S8OtKKgT/fRwLQ== X-IronPort-AV: E=McAfee;i="6700,10204,11136"; a="29996348" X-IronPort-AV: E=Sophos;i="6.09,217,1716274800"; d="scan'208";a="29996348" X-CSE-ConnectionGUID: h+KDg8LFQnyOCWs4bTTNyQ== X-CSE-MsgGUID: P8+khh/SR5m4omxyJtxAVA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,217,1716274800"; d="scan'208";a="81717438" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, peterx@redhat.com, jasowang@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Zhenzhong Duan , Marcel Apfelbaum , Paolo Bonzini , Richard Henderson , Eduardo Habkost Subject: [PATCH v1 11/17] intel_iommu: Extract device IOTLB invalidation logic Date: Thu, 18 Jul 2024 16:16:30 +0800 Message-Id: <20240718081636.879544-12-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240718081636.879544-1-zhenzhong.duan@intel.com> References: <20240718081636.879544-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.13; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1721290881150116600 From: Cl=C3=A9ment Mathieu--Drif This piece of code can be shared by both IOTLB invalidation and PASID-based IOTLB invalidation No functional changes intended. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Cl=C3=A9ment Mathieu--Drif Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu.c | 57 +++++++++++++++++++++++++------------------ 1 file changed, 33 insertions(+), 24 deletions(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 8ebb6dbd7d..4d5a457f92 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -2975,13 +2975,43 @@ static bool vtd_process_inv_iec_desc(IntelIOMMUStat= e *s, return true; } =20 +static void do_invalidate_device_tlb(VTDAddressSpace *vtd_dev_as, + bool size, hwaddr addr) +{ + /* + * According to ATS spec table 2.4: + * S =3D 0, bits 15:12 =3D xxxx range size: 4K + * S =3D 1, bits 15:12 =3D xxx0 range size: 8K + * S =3D 1, bits 15:12 =3D xx01 range size: 16K + * S =3D 1, bits 15:12 =3D x011 range size: 32K + * S =3D 1, bits 15:12 =3D 0111 range size: 64K + * ... + */ + + IOMMUTLBEvent event; + uint64_t sz; + + if (size) { + sz =3D (VTD_PAGE_SIZE * 2) << cto64(addr >> VTD_PAGE_SHIFT); + addr &=3D ~(sz - 1); + } else { + sz =3D VTD_PAGE_SIZE; + } + + event.type =3D IOMMU_NOTIFIER_DEVIOTLB_UNMAP; + event.entry.target_as =3D &vtd_dev_as->as; + event.entry.addr_mask =3D sz - 1; + event.entry.iova =3D addr; + event.entry.perm =3D IOMMU_NONE; + event.entry.translated_addr =3D 0; + memory_region_notify_iommu(&vtd_dev_as->iommu, 0, event); +} + static bool vtd_process_device_iotlb_desc(IntelIOMMUState *s, VTDInvDesc *inv_desc) { VTDAddressSpace *vtd_dev_as; - IOMMUTLBEvent event; hwaddr addr; - uint64_t sz; uint16_t sid; bool size; =20 @@ -3006,28 +3036,7 @@ static bool vtd_process_device_iotlb_desc(IntelIOMMU= State *s, goto done; } =20 - /* According to ATS spec table 2.4: - * S =3D 0, bits 15:12 =3D xxxx range size: 4K - * S =3D 1, bits 15:12 =3D xxx0 range size: 8K - * S =3D 1, bits 15:12 =3D xx01 range size: 16K - * S =3D 1, bits 15:12 =3D x011 range size: 32K - * S =3D 1, bits 15:12 =3D 0111 range size: 64K - * ... - */ - if (size) { - sz =3D (VTD_PAGE_SIZE * 2) << cto64(addr >> VTD_PAGE_SHIFT); - addr &=3D ~(sz - 1); - } else { - sz =3D VTD_PAGE_SIZE; - } - - event.type =3D IOMMU_NOTIFIER_DEVIOTLB_UNMAP; - event.entry.target_as =3D &vtd_dev_as->as; - event.entry.addr_mask =3D sz - 1; - event.entry.iova =3D addr; - event.entry.perm =3D IOMMU_NONE; - event.entry.translated_addr =3D 0; - memory_region_notify_iommu(&vtd_dev_as->iommu, 0, event); + do_invalidate_device_tlb(vtd_dev_as, size, addr); =20 done: return true; --=20 2.34.1 From nobody Mon Sep 16 19:12:33 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1721290897; cv=none; d=zohomail.com; s=zohoarc; b=JaRxN0gDiqS0XGusnAbrhfeB1BJnEPIDbC1AuETDtFaifvD5yJ3tyoZrVFru/BS1vA4eZPG+cqXi7U0Ei4k+ElBi9kWFEgMh/UVCoA8I5VcUduiF5LULtQAtKfd189idp7abdmApkHcZ10nT1gsvs7QYpKZuIfcpI8h/4ImdTeY= ARC-Message-Signature: i=1; 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bh=mRNgSK+lvPVIQ5ohj2ofuEHvUoQzLamIns1ZSquOD7Y=; b=Kscl3OcWq8bJUbkFYIaRag4OKUJk2vF15tV7ihQdwHzHnGy8JTQjq5pv 43frU+v2Bk34mOssZLk4BRrADVZ+FXAY72734mr6G3l1wrpi6DHexKHkH HBF/aOnU2vUaK9QpZ5TodIPgEZg7yBHAfLCT8kykrZUS2SvFxSw0cqKC6 EiftoRP2mcH+OKJYWGZE/gRU7MR5zih6o93AWM6ICo6QhQnjJvI16AhAj QAkmLZSHOmOZr3YxvGCtN7a534DEmO+/IAYWOxBuTvhI2l+j9U883jMWi lrg5aeAPp0Tx9bPk+2hDZ7XZMz+nkrl1Di9Z+FEy5LGfosesT1ZjEp7ng w==; X-CSE-ConnectionGUID: bb8vW+X5T9qYVyrkEeQipA== X-CSE-MsgGUID: 32HLydaLQXiU2ZGUczD9Xw== X-IronPort-AV: E=McAfee;i="6700,10204,11136"; a="29996363" X-IronPort-AV: E=Sophos;i="6.09,217,1716274800"; d="scan'208";a="29996363" X-CSE-ConnectionGUID: akdQARxoQgqm5tBu8Zqhyw== X-CSE-MsgGUID: FUUfwgZTTXSckWYJtHGlwQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,217,1716274800"; d="scan'208";a="81717463" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, peterx@redhat.com, jasowang@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Zhenzhong Duan , Marcel Apfelbaum , Paolo Bonzini , Richard Henderson , Eduardo Habkost Subject: [PATCH v1 12/17] intel_iommu: Add an internal API to find an address space with PASID Date: Thu, 18 Jul 2024 16:16:31 +0800 Message-Id: <20240718081636.879544-13-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240718081636.879544-1-zhenzhong.duan@intel.com> References: <20240718081636.879544-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.13; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1721290899217116600 From: Cl=C3=A9ment Mathieu--Drif This will be used to implement the device IOTLB invalidation Signed-off-by: Cl=C3=A9ment Mathieu--Drif Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu.c | 39 ++++++++++++++++++++++++--------------- 1 file changed, 24 insertions(+), 15 deletions(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 4d5a457f92..a17ce2b1f1 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -70,6 +70,11 @@ struct vtd_hiod_key { uint8_t devfn; }; =20 +struct vtd_as_raw_key { + uint16_t sid; + uint32_t pasid; +}; + struct vtd_iotlb_key { uint64_t gfn; uint32_t pasid; @@ -1878,29 +1883,33 @@ static inline bool vtd_is_interrupt_addr(hwaddr add= r) return VTD_INTERRUPT_ADDR_FIRST <=3D addr && addr <=3D VTD_INTERRUPT_A= DDR_LAST; } =20 -static gboolean vtd_find_as_by_sid(gpointer key, gpointer value, - gpointer user_data) +static gboolean vtd_find_as_by_sid_and_pasid(gpointer key, gpointer value, + gpointer user_data) { struct vtd_as_key *as_key =3D (struct vtd_as_key *)key; - uint16_t target_sid =3D *(uint16_t *)user_data; + struct vtd_as_raw_key target =3D *(struct vtd_as_raw_key *)user_data; uint16_t sid =3D PCI_BUILD_BDF(pci_bus_num(as_key->bus), as_key->devfn= ); - return sid =3D=3D target_sid; + + return (as_key->pasid =3D=3D target.pasid) && + (sid =3D=3D target.sid); } =20 -static VTDAddressSpace *vtd_get_as_by_sid(IntelIOMMUState *s, uint16_t sid) +static VTDAddressSpace *vtd_get_as_by_sid_and_pasid(IntelIOMMUState *s, + uint16_t sid, + uint32_t pasid) { - uint8_t bus_num =3D PCI_BUS_NUM(sid); - VTDAddressSpace *vtd_as =3D s->vtd_as_cache[bus_num]; - - if (vtd_as && - (sid =3D=3D PCI_BUILD_BDF(pci_bus_num(vtd_as->bus), vtd_as->devfn)= )) { - return vtd_as; - } + struct vtd_as_raw_key key =3D { + .sid =3D sid, + .pasid =3D pasid + }; =20 - vtd_as =3D g_hash_table_find(s->vtd_address_spaces, vtd_find_as_by_sid= , &sid); - s->vtd_as_cache[bus_num] =3D vtd_as; + return g_hash_table_find(s->vtd_address_spaces, + vtd_find_as_by_sid_and_pasid, &key); +} =20 - return vtd_as; +static VTDAddressSpace *vtd_get_as_by_sid(IntelIOMMUState *s, uint16_t sid) +{ + return vtd_get_as_by_sid_and_pasid(s, sid, PCI_NO_PASID); } =20 static void vtd_pt_enable_fast_path(IntelIOMMUState *s, uint16_t source_id) --=20 2.34.1 From nobody Mon Sep 16 19:12:33 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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d="scan'208";a="81717490" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, peterx@redhat.com, jasowang@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Zhenzhong Duan , Marcel Apfelbaum , Paolo Bonzini , Richard Henderson , Eduardo Habkost Subject: [PATCH v1 13/17] intel_iommu: Add support for PASID-based device IOTLB invalidation Date: Thu, 18 Jul 2024 16:16:32 +0800 Message-Id: <20240718081636.879544-14-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240718081636.879544-1-zhenzhong.duan@intel.com> References: <20240718081636.879544-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.13; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1721290869363116600 From: Cl=C3=A9ment Mathieu--Drif Signed-off-by: Cl=C3=A9ment Mathieu--Drif Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu_internal.h | 11 ++++++++ hw/i386/intel_iommu.c | 50 ++++++++++++++++++++++++++++++++++ 2 files changed, 61 insertions(+) diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h index 7dd8176e86..ed358aa763 100644 --- a/hw/i386/intel_iommu_internal.h +++ b/hw/i386/intel_iommu_internal.h @@ -377,6 +377,7 @@ typedef union VTDInvDesc VTDInvDesc; #define VTD_INV_DESC_WAIT 0x5 /* Invalidation Wait Descripto= r */ #define VTD_INV_DESC_PIOTLB 0x6 /* PASID-IOTLB Invalidate Desc= */ #define VTD_INV_DESC_PC 0x7 /* PASID-cache Invalidate Desc= */ +#define VTD_INV_DESC_DEV_PIOTLB 0x8 /* PASID-based-DIOTLB inv_desc= */ #define VTD_INV_DESC_NONE 0 /* Not an Invalidate Descripto= r */ =20 /* Masks for Invalidation Wait Descriptor*/ @@ -420,6 +421,16 @@ typedef union VTDInvDesc VTDInvDesc; #define VTD_INV_DESC_DEVICE_IOTLB_RSVD_HI 0xffeULL #define VTD_INV_DESC_DEVICE_IOTLB_RSVD_LO 0xffff0000ffe0fff8 =20 +/* Mask for PASID Device IOTLB Invalidate Descriptor */ +#define VTD_INV_DESC_PASID_DEVICE_IOTLB_ADDR(val) ((val) & \ + 0xfffffffffffff000ULL) +#define VTD_INV_DESC_PASID_DEVICE_IOTLB_SIZE(val) ((val >> 11) & 0x1) +#define VTD_INV_DESC_PASID_DEVICE_IOTLB_GLOBAL(val) ((val) & 0x1) +#define VTD_INV_DESC_PASID_DEVICE_IOTLB_SID(val) (((val) >> 16) & 0xffffUL= L) +#define VTD_INV_DESC_PASID_DEVICE_IOTLB_PASID(val) ((val >> 32) & 0xfffffU= LL) +#define VTD_INV_DESC_PASID_DEVICE_IOTLB_RSVD_HI 0x7feULL +#define VTD_INV_DESC_PASID_DEVICE_IOTLB_RSVD_LO 0xfff000000000f000ULL + /* Rsvd field masks for spte */ #define VTD_SPTE_SNP 0x800ULL =20 diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index a17ce2b1f1..8b66d6cfa5 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -3016,6 +3016,49 @@ static void do_invalidate_device_tlb(VTDAddressSpace= *vtd_dev_as, memory_region_notify_iommu(&vtd_dev_as->iommu, 0, event); } =20 +static bool vtd_process_device_piotlb_desc(IntelIOMMUState *s, + VTDInvDesc *inv_desc) +{ + uint16_t sid; + VTDAddressSpace *vtd_dev_as; + bool size; + bool global; + hwaddr addr; + uint32_t pasid; + + if ((inv_desc->hi & VTD_INV_DESC_PASID_DEVICE_IOTLB_RSVD_HI) || + (inv_desc->lo & VTD_INV_DESC_PASID_DEVICE_IOTLB_RSVD_LO)) { + error_report_once("%s: invalid pasid-based dev iotlb inv desc:" + "hi=3D%"PRIx64 "(reserved nonzero)", + __func__, inv_desc->hi); + return false; + } + + global =3D VTD_INV_DESC_PASID_DEVICE_IOTLB_GLOBAL(inv_desc->hi); + size =3D VTD_INV_DESC_PASID_DEVICE_IOTLB_SIZE(inv_desc->hi); + addr =3D VTD_INV_DESC_PASID_DEVICE_IOTLB_ADDR(inv_desc->hi); + sid =3D VTD_INV_DESC_PASID_DEVICE_IOTLB_SID(inv_desc->lo); + if (global) { + QLIST_FOREACH(vtd_dev_as, &s->vtd_as_with_notifiers, next) { + if ((vtd_dev_as->pasid !=3D PCI_NO_PASID) && + (PCI_BUILD_BDF(pci_bus_num(vtd_dev_as->bus), + vtd_dev_as->devfn) =3D=3D sid))= { + do_invalidate_device_tlb(vtd_dev_as, size, addr); + } + } + } else { + pasid =3D VTD_INV_DESC_PASID_DEVICE_IOTLB_PASID(inv_desc->lo); + vtd_dev_as =3D vtd_get_as_by_sid_and_pasid(s, sid, pasid); + if (!vtd_dev_as) { + return true; + } + + do_invalidate_device_tlb(vtd_dev_as, size, addr); + } + + return true; +} + static bool vtd_process_device_iotlb_desc(IntelIOMMUState *s, VTDInvDesc *inv_desc) { @@ -3110,6 +3153,13 @@ static bool vtd_process_inv_desc(IntelIOMMUState *s) } break; =20 + case VTD_INV_DESC_DEV_PIOTLB: + trace_vtd_inv_desc("device-piotlb", inv_desc.hi, inv_desc.lo); + if (!vtd_process_device_piotlb_desc(s, &inv_desc)) { + return false; + } + break; + case VTD_INV_DESC_DEVICE: trace_vtd_inv_desc("device", inv_desc.hi, inv_desc.lo); if (!vtd_process_device_iotlb_desc(s, &inv_desc)) { --=20 2.34.1 From nobody Mon Sep 16 19:12:33 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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d="scan'208";a="81717514" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, peterx@redhat.com, jasowang@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Zhenzhong Duan , Yi Sun , Marcel Apfelbaum , Paolo Bonzini , Richard Henderson , Eduardo Habkost Subject: [PATCH v1 14/17] intel_iommu: piotlb invalidation should notify unmap Date: Thu, 18 Jul 2024 16:16:33 +0800 Message-Id: <20240718081636.879544-15-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240718081636.879544-1-zhenzhong.duan@intel.com> References: <20240718081636.879544-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.13; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1721290905230116600 Content-Type: text/plain; charset="utf-8" This is used by some emulated devices which caches address translation result. When piotlb invalidation issued in guest, those caches should be refreshed. Signed-off-by: Yi Sun Signed-off-by: Zhenzhong Duan Reviewed-by: Cl=C3=A9ment Mathieu--Drif --- hw/i386/intel_iommu.c | 35 ++++++++++++++++++++++++++++++++++- 1 file changed, 34 insertions(+), 1 deletion(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 8b66d6cfa5..c0116497b1 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -2910,7 +2910,7 @@ static void vtd_piotlb_pasid_invalidate(IntelIOMMUSta= te *s, continue; } =20 - if (!s->scalable_modern) { + if (!s->scalable_modern || !vtd_as_has_map_notifier(vtd_as)) { vtd_address_space_sync(vtd_as); } } @@ -2922,6 +2922,9 @@ static void vtd_piotlb_page_invalidate(IntelIOMMUStat= e *s, uint16_t domain_id, bool ih) { VTDIOTLBPageInvInfo info; + VTDAddressSpace *vtd_as; + VTDContextEntry ce; + hwaddr size =3D (1 << am) * VTD_PAGE_SIZE; =20 info.domain_id =3D domain_id; info.pasid =3D pasid; @@ -2932,6 +2935,36 @@ static void vtd_piotlb_page_invalidate(IntelIOMMUSta= te *s, uint16_t domain_id, g_hash_table_foreach_remove(s->iotlb, vtd_hash_remove_by_page_piotlb, &info); vtd_iommu_unlock(s); + + QLIST_FOREACH(vtd_as, &s->vtd_as_with_notifiers, next) { + if (!vtd_dev_to_context_entry(s, pci_bus_num(vtd_as->bus), + vtd_as->devfn, &ce) && + domain_id =3D=3D vtd_get_domain_id(s, &ce, vtd_as->pasid)) { + uint32_t rid2pasid =3D VTD_CE_GET_RID2PASID(&ce); + IOMMUTLBEvent event; + + if ((vtd_as->pasid !=3D PCI_NO_PASID || pasid !=3D rid2pasid) = && + vtd_as->pasid !=3D pasid) { + continue; + } + + /* + * Page-Selective-within-PASID PASID-based-IOTLB Invalidation + * does not flush stage-2 entries. See spec section 6.5.2.4 + */ + if (!s->scalable_modern) { + continue; + } + + event.type =3D IOMMU_NOTIFIER_UNMAP; + event.entry.target_as =3D &address_space_memory; + event.entry.iova =3D addr; + event.entry.perm =3D IOMMU_NONE; + event.entry.addr_mask =3D size - 1; + event.entry.translated_addr =3D 0; + memory_region_notify_iommu(&vtd_as->iommu, 0, event); + } + } } =20 static bool vtd_process_piotlb_desc(IntelIOMMUState *s, --=20 2.34.1 From nobody Mon Sep 16 19:12:33 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1721290898; cv=none; d=zohomail.com; s=zohoarc; b=SMRznWVgpAJgCpHbSNZHO/pruBaFnJsHgtyC26lhsRi+89inQH8eW598Vzrv6VA+0CvnzKelQWr0EPm0XBblDeO/6D3PkTp3KCbt/eORHAemataWne+0BEm6bBNKnVq3pgX6kT9xN8erd1BHhxLLf0Zi8kUIYAHHU1/qbLZhsis= ARC-Message-Signature: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.13; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1721290899228116600 Content-Type: text/plain; charset="utf-8" According to VTD spec, stage-1 page table could support 4-level and 5-level paging. However, 5-level paging translation emulation is unsupported yet. That means the only supported value for aw_bits is 48. So default aw_bits to 48 in scalable modern mode. In other cases, it is still default to 39 for compatibility. Add a check to ensure user specified value is 48 in modern mode for now. Signed-off-by: Zhenzhong Duan Reviewed-by: Cl=C3=A9ment Mathieu--Drif --- include/hw/i386/intel_iommu.h | 2 +- hw/i386/intel_iommu.c | 16 +++++++++++++++- 2 files changed, 16 insertions(+), 2 deletions(-) diff --git a/include/hw/i386/intel_iommu.h b/include/hw/i386/intel_iommu.h index b843d069cc..48134bda11 100644 --- a/include/hw/i386/intel_iommu.h +++ b/include/hw/i386/intel_iommu.h @@ -45,7 +45,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(IntelIOMMUState, INTEL_IOMMU_D= EVICE) #define DMAR_REG_SIZE 0x230 #define VTD_HOST_AW_39BIT 39 #define VTD_HOST_AW_48BIT 48 -#define VTD_HOST_ADDRESS_WIDTH VTD_HOST_AW_39BIT +#define VTD_HOST_AW_AUTO 0xff #define VTD_HAW_MASK(aw) ((1ULL << (aw)) - 1) =20 #define DMAR_REPORT_F_INTR (1) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index c0116497b1..2804c3628a 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -3768,7 +3768,7 @@ static Property vtd_properties[] =3D { ON_OFF_AUTO_AUTO), DEFINE_PROP_BOOL("x-buggy-eim", IntelIOMMUState, buggy_eim, false), DEFINE_PROP_UINT8("aw-bits", IntelIOMMUState, aw_bits, - VTD_HOST_ADDRESS_WIDTH), + VTD_HOST_AW_AUTO), DEFINE_PROP_BOOL("caching-mode", IntelIOMMUState, caching_mode, FALSE), DEFINE_PROP_BOOL("x-scalable-mode", IntelIOMMUState, scalable_mode, FA= LSE), DEFINE_PROP_BOOL("snoop-control", IntelIOMMUState, snoop_control, fals= e), @@ -4686,6 +4686,14 @@ static bool vtd_decide_config(IntelIOMMUState *s, Er= ror **errp) } } =20 + if (s->aw_bits =3D=3D VTD_HOST_AW_AUTO) { + if (s->scalable_modern) { + s->aw_bits =3D VTD_HOST_AW_48BIT; + } else { + s->aw_bits =3D VTD_HOST_AW_39BIT; + } + } + if ((s->aw_bits !=3D VTD_HOST_AW_39BIT) && (s->aw_bits !=3D VTD_HOST_AW_48BIT) && !s->scalable_modern) { @@ -4694,6 +4702,12 @@ static bool vtd_decide_config(IntelIOMMUState *s, Er= ror **errp) return false; } =20 + if ((s->aw_bits !=3D VTD_HOST_AW_48BIT) && s->scalable_modern) { + error_setg(errp, "Supported values for aw-bits are: %d", + VTD_HOST_AW_48BIT); + return false; + } + if (s->scalable_mode && !s->dma_drain) { error_setg(errp, "Need to set dma_drain for scalable mode"); return false; --=20 2.34.1 From nobody Mon Sep 16 19:12:33 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1721290877; cv=none; d=zohomail.com; s=zohoarc; b=YrtfTNnQx+Zy38VokbEeRqIqsd0FtYsiD3GE4A+abUglPDsm7PhQVXJrzz6idxnZndi0SeCSlv6A1S7e6anX3VwWMF/g9EX4KYXJd+cPAKRZHrGzQywJv5QBAztBgFSEcUkdHlrJuFiyTfODA2BqUkOeKVibV+QWNpta6Fnvmp0= ARC-Message-Signature: i=1; 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bh=Ea9w0E1SFOmJEvDucd0WLrDduqllD5j3200E39hZKMk=; b=hrAAppd/h9KCwbRyB08gWb/lWT+P2+MJ3RxBo4Twv6g20LJmMW3S685s EPD18ev4f601lFw7Rw7vgEf9APesqtYIUDaghQkFANaSfdCT3U65EDwLq 7lEyB2SwCNiCpgTMTNW57xyc/Z2HtRiPiaSKeD95Hi6EjNCIXwg6udhu8 ijhZyYJrduO8aL9J02o1Vy2qPTp+CQyiZqQ4IznjCeFp+GKfEHWOsxun0 erDGK2fVj0XaU9TdL32N2xZJCh4gQsyTVQxCZJKl6l35TPMnwG8FF02+b OR2EJ6CTvP1NFTwpJLAcBPFCy4qwG7z8n9aRHBCLlBrod4kqGwrWSdOPM Q==; X-CSE-ConnectionGUID: EM0s9o07Qpa1LJJ0B90/5Q== X-CSE-MsgGUID: SQec3n24SR2s57yf4QvdLg== X-IronPort-AV: E=McAfee;i="6700,10204,11136"; a="29996422" X-IronPort-AV: E=Sophos;i="6.09,217,1716274800"; d="scan'208";a="29996422" X-CSE-ConnectionGUID: KjMlPidAQNCTIH9SaPtHZQ== X-CSE-MsgGUID: 7T+hyVsLT1KkE5wJmhVJcw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,217,1716274800"; d="scan'208";a="81717591" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, peterx@redhat.com, jasowang@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Yi Sun , Zhenzhong Duan , Marcel Apfelbaum , Paolo Bonzini , Richard Henderson , Eduardo Habkost Subject: [PATCH v1 16/17] intel_iommu: Modify x-scalable-mode to be string option Date: Thu, 18 Jul 2024 16:16:35 +0800 Message-Id: <20240718081636.879544-17-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240718081636.879544-1-zhenzhong.duan@intel.com> References: <20240718081636.879544-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.13; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1721290879129116600 Content-Type: text/plain; charset="utf-8" From: Yi Liu Intel VT-d 3.0 introduces scalable mode, and it has a bunch of capabilities related to scalable mode translation, thus there are multiple combinations. While this vIOMMU implementation wants to simplify it for user by providing typical combinations. User could config it by "x-scalable-mode" option. The usage is as below: "-device intel-iommu,x-scalable-mode=3D["legacy"|"modern"|"off"]" - "legacy": gives support for stage-2 page table - "modern": gives support for stage-1 page table - "off": no scalable mode support - if not configured, means no scalable mode support, if not proper configured, will throw error Signed-off-by: Yi Liu Signed-off-by: Yi Sun Signed-off-by: Zhenzhong Duan --- include/hw/i386/intel_iommu.h | 1 + hw/i386/intel_iommu.c | 24 +++++++++++++++++++++++- 2 files changed, 24 insertions(+), 1 deletion(-) diff --git a/include/hw/i386/intel_iommu.h b/include/hw/i386/intel_iommu.h index 48134bda11..650641544c 100644 --- a/include/hw/i386/intel_iommu.h +++ b/include/hw/i386/intel_iommu.h @@ -263,6 +263,7 @@ struct IntelIOMMUState { =20 bool caching_mode; /* RO - is cap CM enabled? */ bool scalable_mode; /* RO - is Scalable Mode supported? */ + char *scalable_mode_str; /* RO - admin's Scalable Mode config */ bool scalable_modern; /* RO - is modern SM supported? */ bool snoop_control; /* RO - is SNP filed supported? */ =20 diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 2804c3628a..14d05fce1d 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -3770,7 +3770,7 @@ static Property vtd_properties[] =3D { DEFINE_PROP_UINT8("aw-bits", IntelIOMMUState, aw_bits, VTD_HOST_AW_AUTO), DEFINE_PROP_BOOL("caching-mode", IntelIOMMUState, caching_mode, FALSE), - DEFINE_PROP_BOOL("x-scalable-mode", IntelIOMMUState, scalable_mode, FA= LSE), + DEFINE_PROP_STRING("x-scalable-mode", IntelIOMMUState, scalable_mode_s= tr), DEFINE_PROP_BOOL("snoop-control", IntelIOMMUState, snoop_control, fals= e), DEFINE_PROP_BOOL("x-pasid-mode", IntelIOMMUState, pasid, false), DEFINE_PROP_BOOL("dma-drain", IntelIOMMUState, dma_drain, true), @@ -4686,6 +4686,28 @@ static bool vtd_decide_config(IntelIOMMUState *s, Er= ror **errp) } } =20 + if (s->scalable_mode_str && + (strcmp(s->scalable_mode_str, "off") && + strcmp(s->scalable_mode_str, "modern") && + strcmp(s->scalable_mode_str, "legacy"))) { + error_setg(errp, "Invalid x-scalable-mode config," + "Please use \"modern\", \"legacy\" or \"off\""); + return false; + } + + if (s->scalable_mode_str && + !strcmp(s->scalable_mode_str, "legacy")) { + s->scalable_mode =3D true; + s->scalable_modern =3D false; + } else if (s->scalable_mode_str && + !strcmp(s->scalable_mode_str, "modern")) { + s->scalable_mode =3D true; + s->scalable_modern =3D true; + } else { + s->scalable_mode =3D false; + s->scalable_modern =3D false; + } + if (s->aw_bits =3D=3D VTD_HOST_AW_AUTO) { if (s->scalable_modern) { s->aw_bits =3D VTD_HOST_AW_48BIT; --=20 2.34.1 From nobody Mon Sep 16 19:12:33 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1721290928; cv=none; d=zohomail.com; s=zohoarc; b=barNOzGKwirKQoU84FHFbNiVtTLP1EKoiCDuPV7tsJJkWL1IQMfMzcgNefjMvFm0pbdlfLFbzVAUaaPswjRaaEg5LnDoYX91p5gVZVERfypmxFEemzPj6rfFCBevH4hXMTyWPqfFRKV5JiaH2bpRe/BUnHgmtFkUUsAI9bfNxHU= ARC-Message-Signature: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.13; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1721290929434116600 Content-Type: text/plain; charset="utf-8" Add the framework to test the intel-iommu device. Currently only tested cap/ecap bits correctness in scalable modern mode. Also tested cap/ecap bits consistency before and after system reset. Signed-off-by: Zhenzhong Duan Reviewed-by: Cl=C3=A9ment Mathieu--Drif --- MAINTAINERS | 1 + include/hw/i386/intel_iommu.h | 1 + tests/qtest/intel-iommu-test.c | 71 ++++++++++++++++++++++++++++++++++ tests/qtest/meson.build | 1 + 4 files changed, 74 insertions(+) create mode 100644 tests/qtest/intel-iommu-test.c diff --git a/MAINTAINERS b/MAINTAINERS index 7d9811458c..ec765bf3d3 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3662,6 +3662,7 @@ S: Supported F: hw/i386/intel_iommu.c F: hw/i386/intel_iommu_internal.h F: include/hw/i386/intel_iommu.h +F: tests/qtest/intel-iommu-test.c =20 AMD-Vi Emulation S: Orphan diff --git a/include/hw/i386/intel_iommu.h b/include/hw/i386/intel_iommu.h index 650641544c..b1848dbec6 100644 --- a/include/hw/i386/intel_iommu.h +++ b/include/hw/i386/intel_iommu.h @@ -47,6 +47,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(IntelIOMMUState, INTEL_IOMMU_D= EVICE) #define VTD_HOST_AW_48BIT 48 #define VTD_HOST_AW_AUTO 0xff #define VTD_HAW_MASK(aw) ((1ULL << (aw)) - 1) +#define VTD_MGAW_FROM_CAP(cap) ((cap >> 16) & 0x3fULL) =20 #define DMAR_REPORT_F_INTR (1) =20 diff --git a/tests/qtest/intel-iommu-test.c b/tests/qtest/intel-iommu-test.c new file mode 100644 index 0000000000..8e07034f6f --- /dev/null +++ b/tests/qtest/intel-iommu-test.c @@ -0,0 +1,71 @@ +/* + * QTest testcase for intel-iommu + * + * Copyright (c) 2024 Intel, Inc. + * + * Author: Zhenzhong Duan + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "libqtest.h" +#include "hw/i386/intel_iommu_internal.h" + +#define CAP_MODERN_FIXED1 (VTD_CAP_FRO | VTD_CAP_NFR | VTD_CAP_ND | \ + VTD_CAP_MAMV | VTD_CAP_PSI | VTD_CAP_SLLPS) +#define ECAP_MODERN_FIXED1 (VTD_ECAP_QI | VTD_ECAP_IRO | VTD_ECAP_MHMV = | \ + VTD_ECAP_SMTS | VTD_ECAP_FLTS) + +static inline uint32_t vtd_reg_readl(QTestState *s, uint64_t offset) +{ + return qtest_readl(s, Q35_HOST_BRIDGE_IOMMU_ADDR + offset); +} + +static inline uint64_t vtd_reg_readq(QTestState *s, uint64_t offset) +{ + return qtest_readq(s, Q35_HOST_BRIDGE_IOMMU_ADDR + offset); +} + +static void test_intel_iommu_modern(void) +{ + uint8_t init_csr[DMAR_REG_SIZE]; /* register values */ + uint8_t post_reset_csr[DMAR_REG_SIZE]; /* register values */ + uint64_t cap, ecap, tmp; + QTestState *s; + + s =3D qtest_init("-M q35 -device intel-iommu,x-scalable-mode=3Dmodern"= ); + + cap =3D vtd_reg_readq(s, DMAR_CAP_REG); + g_assert((cap & CAP_MODERN_FIXED1) =3D=3D CAP_MODERN_FIXED1); + + tmp =3D cap & VTD_CAP_SAGAW_MASK; + g_assert(tmp =3D=3D (VTD_CAP_SAGAW_39bit | VTD_CAP_SAGAW_48bit)); + + tmp =3D VTD_MGAW_FROM_CAP(cap); + g_assert(tmp =3D=3D VTD_HOST_AW_48BIT - 1); + + ecap =3D vtd_reg_readq(s, DMAR_ECAP_REG); + g_assert((ecap & ECAP_MODERN_FIXED1) =3D=3D ECAP_MODERN_FIXED1); + g_assert(ecap & VTD_ECAP_IR); + + qtest_memread(s, Q35_HOST_BRIDGE_IOMMU_ADDR, init_csr, DMAR_REG_SIZE); + + qobject_unref(qtest_qmp(s, "{ 'execute': 'system_reset' }")); + qtest_qmp_eventwait(s, "RESET"); + + qtest_memread(s, Q35_HOST_BRIDGE_IOMMU_ADDR, post_reset_csr, DMAR_REG_= SIZE); + /* Ensure registers are consistent after hard reset */ + g_assert(!memcmp(init_csr, post_reset_csr, DMAR_REG_SIZE)); + + qtest_quit(s); +} + +int main(int argc, char **argv) +{ + g_test_init(&argc, &argv, NULL); + qtest_add_func("/q35/intel-iommu/modern", test_intel_iommu_modern); + + return g_test_run(); +} diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index 6508bfb1a2..20d05d471b 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -79,6 +79,7 @@ qtests_i386 =3D \ (config_all_devices.has_key('CONFIG_SB16') ? ['fuzz-sb16-test'] : []) + = \ (config_all_devices.has_key('CONFIG_SDHCI_PCI') ? ['fuzz-sdcard-test'] := []) + \ (config_all_devices.has_key('CONFIG_ESP_PCI') ? ['am53c974-test'] : []) = + \ + (config_all_devices.has_key('CONFIG_VTD') ? ['intel-iommu-test'] : []) += \ (host_os !=3D 'windows' and = \ config_all_devices.has_key('CONFIG_ACPI_ERST') ? ['erst-test'] : []) + = \ (config_all_devices.has_key('CONFIG_PCIE_PORT') and = \ --=20 2.34.1