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[2403:580b:97e8:0:82ce:f179:8a79:69f4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1fc0bba949bsm81999385ad.69.2024.07.17.19.11.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Jul 2024 19:11:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1721268681; x=1721873481; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=4NdenwwcemciAx5XYGTqEB0Vd6aa6AeSqR/oYgqPmso=; b=j6V1xSn/avqwrnSfFi0JYlhr88bKenaguUr8dPoXmK5BhNT68NVb6Jy/pFuV1PZJhz QznGtK2Ai7Q1k+Lv1IcUV9dZHUlyUJyn2AldflG34w8BZvixMOJ2k0WssQydRNu5P0YR qkX4UsUi9+3lDEp7K0Um5Izy3nW0poOrBKi3gyM1NcQNPsX1cnkh8BHsQZzVDEAjulum h5lokE5aGWntFaX4auUssMAwXHh40iU8/n1pcXnORcuIC/HblBUOKo2MznK2R9O0g6ch 71LSoodzFaxKfY3cC5soUweuhfckpkWs5FF3ScaSJpmVYJAojxSDW6BAu45Ml2YvPVXp Gd2Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1721268681; x=1721873481; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4NdenwwcemciAx5XYGTqEB0Vd6aa6AeSqR/oYgqPmso=; b=BLpCT9MvWQwDkfKNK+UeLBK99ns7wMBzrIJX+ZtTmdnsYUcFStuUs/PyOAvQbwnXkQ +bsVKFe0lZUc8jkQisjWM8EYPESkzf6rThhbOHaZXQHWGpmfFYKo3qI5vXdPkyvcyhy0 24c9COjDGaVrIqgYHlEAJa51AyKUSHA9+XcHUR+bqNUfPraZfnSTnZTmWQZy/nUma+wm eCkHtMY9tz2bvth9Qi2To0BNDPVhempGRBelPFOUWtBk/oq3XpjbXs9alhSqqVtnsuJi 0xs09O1O73ljcOTECaa7Q1TtSk9fTDWVjV/SZb/UjwVUbAOH03vHJAMjNH82uEaNY+8R NFaQ== X-Gm-Message-State: AOJu0YxxQdz1E0++3yLDsko9Oty++aOps4nDRpJxmjQTNggM03qTgLmp 7zP8ynTJw88ZRlj/kbuOvH4Mszil2Hy5DuXuUhTc6YzZQdWo5nXW5hEc18zC X-Google-Smtp-Source: AGHT+IEFNswy+7pQr0A+43ngi8zAMWc1bRsJZdAE6NkKZy6L4iq9eSENnz+/7DERPLcnK9zW6wQlgQ== X-Received: by 2002:a17:902:db0a:b0:1fb:8924:df95 with SMTP id d9443c01a7336-1fc4e56262emr25468795ad.48.1721268680819; Wed, 17 Jul 2024 19:11:20 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Kaiwen Xue , Atish Patra , Daniel Henrique Barboza , Alistair Francis Subject: [PULL 19/30] target/riscv: Add cycle & instret privilege mode filtering support Date: Thu, 18 Jul 2024 12:10:01 +1000 Message-ID: <20240718021012.2057986-20-alistair.francis@wdc.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240718021012.2057986-1-alistair.francis@wdc.com> References: <20240718021012.2057986-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=alistair23@gmail.com; helo=mail-pl1-x629.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1721268702801116600 Content-Type: text/plain; charset="utf-8" From: Kaiwen Xue QEMU only calculates dummy cycles and instructions, so there is no actual means to stop the icount in QEMU. Hence this patch merely adds the functionality of accessing the cfg registers, and cause no actual effects on the counting of cycle and instret counters. Signed-off-by: Atish Patra Reviewed-by: Daniel Henrique Barboza Signed-off-by: Kaiwen Xue Acked-by: Alistair Francis Message-ID: <20240711-smcntrpmf_v7-v8-5-b7c38ae7b263@rivosinc.com> Signed-off-by: Alistair Francis --- target/riscv/cpu_bits.h | 12 ++++ target/riscv/csr.c | 138 +++++++++++++++++++++++++++++++++++++++- 2 files changed, 149 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 5faa817453..32b068f18a 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -926,6 +926,18 @@ typedef enum RISCVException { #define MHPMEVENT_BIT_VUINH BIT_ULL(58) #define MHPMEVENTH_BIT_VUINH BIT(26) =20 +#define MHPMEVENT_FILTER_MASK (MHPMEVENT_BIT_MINH | \ + MHPMEVENT_BIT_SINH | \ + MHPMEVENT_BIT_UINH | \ + MHPMEVENT_BIT_VSINH | \ + MHPMEVENT_BIT_VUINH) + +#define MHPMEVENTH_FILTER_MASK (MHPMEVENTH_BIT_MINH | \ + MHPMEVENTH_BIT_SINH | \ + MHPMEVENTH_BIT_UINH | \ + MHPMEVENTH_BIT_VSINH | \ + MHPMEVENTH_BIT_VUINH) + #define MHPMEVENT_SSCOF_MASK _ULL(0xFFFF000000000000) #define MHPMEVENT_IDX_MASK 0xFFFFF #define MHPMEVENT_SSCOF_RESVD 16 diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 1bcf75f91f..8831d4f5ec 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -30,7 +30,6 @@ #include "qemu/guest-random.h" #include "qapi/error.h" =20 - /* CSR function table public API */ void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops) { @@ -236,6 +235,24 @@ static RISCVException sscofpmf_32(CPURISCVState *env, = int csrno) return sscofpmf(env, csrno); } =20 +static RISCVException smcntrpmf(CPURISCVState *env, int csrno) +{ + if (!riscv_cpu_cfg(env)->ext_smcntrpmf) { + return RISCV_EXCP_ILLEGAL_INST; + } + + return RISCV_EXCP_NONE; +} + +static RISCVException smcntrpmf_32(CPURISCVState *env, int csrno) +{ + if (riscv_cpu_mxl(env) !=3D MXL_RV32) { + return RISCV_EXCP_ILLEGAL_INST; + } + + return smcntrpmf(env, csrno); +} + static RISCVException any(CPURISCVState *env, int csrno) { return RISCV_EXCP_NONE; @@ -830,6 +847,111 @@ static RISCVException read_hpmcounterh(CPURISCVState = *env, int csrno, =20 #else /* CONFIG_USER_ONLY */ =20 +static RISCVException read_mcyclecfg(CPURISCVState *env, int csrno, + target_ulong *val) +{ + *val =3D env->mcyclecfg; + return RISCV_EXCP_NONE; +} + +static RISCVException write_mcyclecfg(CPURISCVState *env, int csrno, + target_ulong val) +{ + uint64_t inh_avail_mask; + + if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { + env->mcyclecfg =3D val; + } else { + /* Set xINH fields if priv mode supported */ + inh_avail_mask =3D ~MHPMEVENT_FILTER_MASK | MCYCLECFG_BIT_MINH; + inh_avail_mask |=3D riscv_has_ext(env, RVU) ? MCYCLECFG_BIT_UINH := 0; + inh_avail_mask |=3D riscv_has_ext(env, RVS) ? MCYCLECFG_BIT_SINH := 0; + inh_avail_mask |=3D (riscv_has_ext(env, RVH) && + riscv_has_ext(env, RVU)) ? MCYCLECFG_BIT_VUINH = : 0; + inh_avail_mask |=3D (riscv_has_ext(env, RVH) && + riscv_has_ext(env, RVS)) ? MCYCLECFG_BIT_VSINH = : 0; + env->mcyclecfg =3D val & inh_avail_mask; + } + + return RISCV_EXCP_NONE; +} + +static RISCVException read_mcyclecfgh(CPURISCVState *env, int csrno, + target_ulong *val) +{ + *val =3D env->mcyclecfgh; + return RISCV_EXCP_NONE; +} + +static RISCVException write_mcyclecfgh(CPURISCVState *env, int csrno, + target_ulong val) +{ + target_ulong inh_avail_mask =3D (target_ulong)(~MHPMEVENTH_FILTER_MASK= | + MCYCLECFGH_BIT_MINH); + + /* Set xINH fields if priv mode supported */ + inh_avail_mask |=3D riscv_has_ext(env, RVU) ? MCYCLECFGH_BIT_UINH : 0; + inh_avail_mask |=3D riscv_has_ext(env, RVS) ? MCYCLECFGH_BIT_SINH : 0; + inh_avail_mask |=3D (riscv_has_ext(env, RVH) && + riscv_has_ext(env, RVU)) ? MCYCLECFGH_BIT_VUINH : 0; + inh_avail_mask |=3D (riscv_has_ext(env, RVH) && + riscv_has_ext(env, RVS)) ? MCYCLECFGH_BIT_VSINH : 0; + + env->mcyclecfgh =3D val & inh_avail_mask; + return RISCV_EXCP_NONE; +} + +static RISCVException read_minstretcfg(CPURISCVState *env, int csrno, + target_ulong *val) +{ + *val =3D env->minstretcfg; + return RISCV_EXCP_NONE; +} + +static RISCVException write_minstretcfg(CPURISCVState *env, int csrno, + target_ulong val) +{ + uint64_t inh_avail_mask; + + if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { + env->minstretcfg =3D val; + } else { + inh_avail_mask =3D ~MHPMEVENT_FILTER_MASK | MINSTRETCFG_BIT_MINH; + inh_avail_mask |=3D riscv_has_ext(env, RVU) ? MINSTRETCFG_BIT_UINH= : 0; + inh_avail_mask |=3D riscv_has_ext(env, RVS) ? MINSTRETCFG_BIT_SINH= : 0; + inh_avail_mask |=3D (riscv_has_ext(env, RVH) && + riscv_has_ext(env, RVU)) ? MINSTRETCFG_BIT_VUIN= H : 0; + inh_avail_mask |=3D (riscv_has_ext(env, RVH) && + riscv_has_ext(env, RVS)) ? MINSTRETCFG_BIT_VSIN= H : 0; + env->minstretcfg =3D val & inh_avail_mask; + } + return RISCV_EXCP_NONE; +} + +static RISCVException read_minstretcfgh(CPURISCVState *env, int csrno, + target_ulong *val) +{ + *val =3D env->minstretcfgh; + return RISCV_EXCP_NONE; +} + +static RISCVException write_minstretcfgh(CPURISCVState *env, int csrno, + target_ulong val) +{ + target_ulong inh_avail_mask =3D (target_ulong)(~MHPMEVENTH_FILTER_MASK= | + MINSTRETCFGH_BIT_MINH); + + inh_avail_mask |=3D riscv_has_ext(env, RVU) ? MINSTRETCFGH_BIT_UINH : = 0; + inh_avail_mask |=3D riscv_has_ext(env, RVS) ? MINSTRETCFGH_BIT_SINH : = 0; + inh_avail_mask |=3D (riscv_has_ext(env, RVH) && + riscv_has_ext(env, RVU)) ? MINSTRETCFGH_BIT_VUINH := 0; + inh_avail_mask |=3D (riscv_has_ext(env, RVH) && + riscv_has_ext(env, RVS)) ? MINSTRETCFGH_BIT_VSINH := 0; + + env->minstretcfgh =3D val & inh_avail_mask; + return RISCV_EXCP_NONE; +} + static RISCVException read_mhpmevent(CPURISCVState *env, int csrno, target_ulong *val) { @@ -5056,6 +5178,13 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { write_mcountinhibit, .min_priv_ver =3D PRIV_VERSION_1_11_0 }, =20 + [CSR_MCYCLECFG] =3D { "mcyclecfg", smcntrpmf, read_mcyclecfg, + write_mcyclecfg, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_MINSTRETCFG] =3D { "minstretcfg", smcntrpmf, read_minstretcfg, + write_minstretcfg, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_MHPMEVENT3] =3D { "mhpmevent3", any, read_mhpmevent, write_mhpmevent }, [CSR_MHPMEVENT4] =3D { "mhpmevent4", any, read_mhpmevent, @@ -5115,6 +5244,13 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_MHPMEVENT31] =3D { "mhpmevent31", any, read_mhpmevent, write_mhpmevent }, =20 + [CSR_MCYCLECFGH] =3D { "mcyclecfgh", smcntrpmf_32, read_mcyclecf= gh, + write_mcyclecfgh, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, + [CSR_MINSTRETCFGH] =3D { "minstretcfgh", smcntrpmf_32, read_minstret= cfgh, + write_minstretcfgh, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, + [CSR_MHPMEVENT3H] =3D { "mhpmevent3h", sscofpmf_32, read_mhpmev= enth, write_mhpmeventh, .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, --=20 2.45.2