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Tue, 16 Jul 2024 22:04:17 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGXvBz1oM06hkAWVWL9O4bNTPNQx0pS0y8tsgs6K/cbyTMO42x215yz0kHHbgWQsHZIvBJJjw== X-Received: by 2002:a5d:58e7:0:b0:367:9765:b2ae with SMTP id ffacd0b85a97d-3683179cb2bmr333370f8f.61.1721192657331; Tue, 16 Jul 2024 22:04:17 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: Richard Henderson Subject: [PULL 19/20] target/i386/tcg: use X86Access for TSS access Date: Wed, 17 Jul 2024 07:03:29 +0200 Message-ID: <20240717050331.295371-20-pbonzini@redhat.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240717050331.295371-1-pbonzini@redhat.com> References: <20240717050331.295371-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1721192703806116600 Content-Type: text/plain; charset="utf-8" This takes care of probing the vaddr range in advance, and is also faster because it avoids repeated TLB lookups. It also matches the Intel manual better, as it says "Checks that the current (old) TSS, new TSS, and all segment descriptors used in the task switch are paged into system memory"; note however that it's not clear how the processor checks for segment descriptors, and this check is not included in the AMD manual. Reviewed-by: Richard Henderson Signed-off-by: Paolo Bonzini --- target/i386/tcg/seg_helper.c | 110 ++++++++++++++++++----------------- 1 file changed, 58 insertions(+), 52 deletions(-) diff --git a/target/i386/tcg/seg_helper.c b/target/i386/tcg/seg_helper.c index a5d5ce61f59..36d2f089cae 100644 --- a/target/i386/tcg/seg_helper.c +++ b/target/i386/tcg/seg_helper.c @@ -27,6 +27,7 @@ #include "exec/log.h" #include "helper-tcg.h" #include "seg_helper.h" +#include "access.h" =20 #ifdef TARGET_X86_64 #define SET_ESP(val, sp_mask) \ @@ -313,14 +314,15 @@ static int switch_tss_ra(CPUX86State *env, int tss_se= lector, uint32_t e1, uint32_t e2, int source, uint32_t next_eip, uintptr_t retaddr) { - int tss_limit, tss_limit_max, type, old_tss_limit_max, old_type, v1, v= 2, i; + int tss_limit, tss_limit_max, type, old_tss_limit_max, old_type, i; target_ulong tss_base; uint32_t new_regs[8], new_segs[6]; uint32_t new_eflags, new_eip, new_cr3, new_ldt, new_trap; uint32_t old_eflags, eflags_mask; SegmentCache *dt; - int index; + int mmu_index, index; target_ulong ptr; + X86Access old, new; =20 type =3D (e2 >> DESC_TYPE_SHIFT) & 0xf; LOG_PCALL("switch_tss: sel=3D0x%04x type=3D%d src=3D%d\n", tss_selecto= r, type, @@ -374,35 +376,45 @@ static int switch_tss_ra(CPUX86State *env, int tss_se= lector, raise_exception_err_ra(env, EXCP0A_TSS, tss_selector & 0xfffc, ret= addr); } =20 + /* X86Access avoids memory exceptions during the task switch */ + mmu_index =3D cpu_mmu_index_kernel(env); + access_prepare_mmu(&old, env, env->tr.base, old_tss_limit_max, + MMU_DATA_STORE, mmu_index, retaddr); + + if (source =3D=3D SWITCH_TSS_CALL) { + /* Probe for future write of parent task */ + probe_access(env, tss_base, 2, MMU_DATA_STORE, + mmu_index, retaddr); + } + access_prepare_mmu(&new, env, tss_base, tss_limit, + MMU_DATA_LOAD, mmu_index, retaddr); + /* read all the registers from the new TSS */ if (type & 8) { /* 32 bit */ - new_cr3 =3D cpu_ldl_kernel_ra(env, tss_base + 0x1c, retaddr); - new_eip =3D cpu_ldl_kernel_ra(env, tss_base + 0x20, retaddr); - new_eflags =3D cpu_ldl_kernel_ra(env, tss_base + 0x24, retaddr); + new_cr3 =3D access_ldl(&new, tss_base + 0x1c); + new_eip =3D access_ldl(&new, tss_base + 0x20); + new_eflags =3D access_ldl(&new, tss_base + 0x24); for (i =3D 0; i < 8; i++) { - new_regs[i] =3D cpu_ldl_kernel_ra(env, tss_base + (0x28 + i * = 4), - retaddr); + new_regs[i] =3D access_ldl(&new, tss_base + (0x28 + i * 4)); } for (i =3D 0; i < 6; i++) { - new_segs[i] =3D cpu_lduw_kernel_ra(env, tss_base + (0x48 + i *= 4), - retaddr); + new_segs[i] =3D access_ldw(&new, tss_base + (0x48 + i * 4)); } - new_ldt =3D cpu_lduw_kernel_ra(env, tss_base + 0x60, retaddr); - new_trap =3D cpu_ldl_kernel_ra(env, tss_base + 0x64, retaddr); + new_ldt =3D access_ldw(&new, tss_base + 0x60); + new_trap =3D access_ldl(&new, tss_base + 0x64); } else { /* 16 bit */ new_cr3 =3D 0; - new_eip =3D cpu_lduw_kernel_ra(env, tss_base + 0x0e, retaddr); - new_eflags =3D cpu_lduw_kernel_ra(env, tss_base + 0x10, retaddr); + new_eip =3D access_ldw(&new, tss_base + 0x0e); + new_eflags =3D access_ldw(&new, tss_base + 0x10); for (i =3D 0; i < 8; i++) { - new_regs[i] =3D cpu_lduw_kernel_ra(env, tss_base + (0x12 + i *= 2), retaddr); + new_regs[i] =3D access_ldw(&new, tss_base + (0x12 + i * 2)); } for (i =3D 0; i < 4; i++) { - new_segs[i] =3D cpu_lduw_kernel_ra(env, tss_base + (0x22 + i *= 2), - retaddr); + new_segs[i] =3D access_ldw(&new, tss_base + (0x22 + i * 2)); } - new_ldt =3D cpu_lduw_kernel_ra(env, tss_base + 0x2a, retaddr); + new_ldt =3D access_ldw(&new, tss_base + 0x2a); new_segs[R_FS] =3D 0; new_segs[R_GS] =3D 0; new_trap =3D 0; @@ -412,16 +424,6 @@ static int switch_tss_ra(CPUX86State *env, int tss_sel= ector, chapters 12.2.5 and 13.2.4 on how to implement TSS Trap bit */ (void)new_trap; =20 - /* NOTE: we must avoid memory exceptions during the task switch, - so we make dummy accesses before */ - /* XXX: it can still fail in some cases, so a bigger hack is - necessary to valid the TLB after having done the accesses */ - - v1 =3D cpu_ldub_kernel_ra(env, env->tr.base, retaddr); - v2 =3D cpu_ldub_kernel_ra(env, env->tr.base + old_tss_limit_max, retad= dr); - cpu_stb_kernel_ra(env, env->tr.base, v1, retaddr); - cpu_stb_kernel_ra(env, env->tr.base + old_tss_limit_max, v2, retaddr); - /* clear busy bit (it is restartable) */ if (source =3D=3D SWITCH_TSS_JMP || source =3D=3D SWITCH_TSS_IRET) { tss_set_busy(env, env->tr.selector, 0, retaddr); @@ -434,35 +436,35 @@ static int switch_tss_ra(CPUX86State *env, int tss_se= lector, /* save the current state in the old TSS */ if (old_type & 8) { /* 32 bit */ - cpu_stl_kernel_ra(env, env->tr.base + 0x20, next_eip, retaddr); - cpu_stl_kernel_ra(env, env->tr.base + 0x24, old_eflags, retaddr); - cpu_stl_kernel_ra(env, env->tr.base + (0x28 + 0 * 4), env->regs[R_= EAX], retaddr); - cpu_stl_kernel_ra(env, env->tr.base + (0x28 + 1 * 4), env->regs[R_= ECX], retaddr); - cpu_stl_kernel_ra(env, env->tr.base + (0x28 + 2 * 4), env->regs[R_= EDX], retaddr); - cpu_stl_kernel_ra(env, env->tr.base + (0x28 + 3 * 4), env->regs[R_= EBX], retaddr); - cpu_stl_kernel_ra(env, env->tr.base + (0x28 + 4 * 4), env->regs[R_= ESP], retaddr); - cpu_stl_kernel_ra(env, env->tr.base + (0x28 + 5 * 4), env->regs[R_= EBP], retaddr); - cpu_stl_kernel_ra(env, env->tr.base + (0x28 + 6 * 4), env->regs[R_= ESI], retaddr); - cpu_stl_kernel_ra(env, env->tr.base + (0x28 + 7 * 4), env->regs[R_= EDI], retaddr); + access_stl(&old, env->tr.base + 0x20, next_eip); + access_stl(&old, env->tr.base + 0x24, old_eflags); + access_stl(&old, env->tr.base + (0x28 + 0 * 4), env->regs[R_EAX]); + access_stl(&old, env->tr.base + (0x28 + 1 * 4), env->regs[R_ECX]); + access_stl(&old, env->tr.base + (0x28 + 2 * 4), env->regs[R_EDX]); + access_stl(&old, env->tr.base + (0x28 + 3 * 4), env->regs[R_EBX]); + access_stl(&old, env->tr.base + (0x28 + 4 * 4), env->regs[R_ESP]); + access_stl(&old, env->tr.base + (0x28 + 5 * 4), env->regs[R_EBP]); + access_stl(&old, env->tr.base + (0x28 + 6 * 4), env->regs[R_ESI]); + access_stl(&old, env->tr.base + (0x28 + 7 * 4), env->regs[R_EDI]); for (i =3D 0; i < 6; i++) { - cpu_stw_kernel_ra(env, env->tr.base + (0x48 + i * 4), - env->segs[i].selector, retaddr); + access_stw(&old, env->tr.base + (0x48 + i * 4), + env->segs[i].selector); } } else { /* 16 bit */ - cpu_stw_kernel_ra(env, env->tr.base + 0x0e, next_eip, retaddr); - cpu_stw_kernel_ra(env, env->tr.base + 0x10, old_eflags, retaddr); - cpu_stw_kernel_ra(env, env->tr.base + (0x12 + 0 * 2), env->regs[R_= EAX], retaddr); - cpu_stw_kernel_ra(env, env->tr.base + (0x12 + 1 * 2), env->regs[R_= ECX], retaddr); - cpu_stw_kernel_ra(env, env->tr.base + (0x12 + 2 * 2), env->regs[R_= EDX], retaddr); - cpu_stw_kernel_ra(env, env->tr.base + (0x12 + 3 * 2), env->regs[R_= EBX], retaddr); - cpu_stw_kernel_ra(env, env->tr.base + (0x12 + 4 * 2), env->regs[R_= ESP], retaddr); - cpu_stw_kernel_ra(env, env->tr.base + (0x12 + 5 * 2), env->regs[R_= EBP], retaddr); - cpu_stw_kernel_ra(env, env->tr.base + (0x12 + 6 * 2), env->regs[R_= ESI], retaddr); - cpu_stw_kernel_ra(env, env->tr.base + (0x12 + 7 * 2), env->regs[R_= EDI], retaddr); + access_stw(&old, env->tr.base + 0x0e, next_eip); + access_stw(&old, env->tr.base + 0x10, old_eflags); + access_stw(&old, env->tr.base + (0x12 + 0 * 2), env->regs[R_EAX]); + access_stw(&old, env->tr.base + (0x12 + 1 * 2), env->regs[R_ECX]); + access_stw(&old, env->tr.base + (0x12 + 2 * 2), env->regs[R_EDX]); + access_stw(&old, env->tr.base + (0x12 + 3 * 2), env->regs[R_EBX]); + access_stw(&old, env->tr.base + (0x12 + 4 * 2), env->regs[R_ESP]); + access_stw(&old, env->tr.base + (0x12 + 5 * 2), env->regs[R_EBP]); + access_stw(&old, env->tr.base + (0x12 + 6 * 2), env->regs[R_ESI]); + access_stw(&old, env->tr.base + (0x12 + 7 * 2), env->regs[R_EDI]); for (i =3D 0; i < 4; i++) { - cpu_stw_kernel_ra(env, env->tr.base + (0x22 + i * 2), - env->segs[i].selector, retaddr); + access_stw(&old, env->tr.base + (0x22 + i * 2), + env->segs[i].selector); } } =20 @@ -470,7 +472,11 @@ static int switch_tss_ra(CPUX86State *env, int tss_sel= ector, context */ =20 if (source =3D=3D SWITCH_TSS_CALL) { - cpu_stw_kernel_ra(env, tss_base, env->tr.selector, retaddr); + /* + * Thanks to the probe_access above, we know the first two + * bytes addressed by &new are writable too. + */ + access_stw(&new, tss_base, env->tr.selector); new_eflags |=3D NT_MASK; } =20 --=20 2.45.2