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Tue, 16 Jul 2024 09:26:55 -0700 (PDT) From: Nicholas Piggin To: qemu-ppc@nongnu.org Cc: Nicholas Piggin , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20Barrat?= , Harsh Prateek Bora , qemu-devel@nongnu.org Subject: [PATCH v3 08/19] target/ppc: Add helpers to check for SMT sibling threads Date: Wed, 17 Jul 2024 02:26:04 +1000 Message-ID: <20240716162617.32161-9-npiggin@gmail.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240716162617.32161-1-npiggin@gmail.com> References: <20240716162617.32161-1-npiggin@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=npiggin@gmail.com; helo=mail-pf1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1721147481381116600 Content-Type: text/plain; charset="utf-8" Add helpers for TCG code to determine if there are SMT siblings sharing per-core and per-lpar registers. This simplifies the callers and makes SMT register topology simpler to modify with later changes. Reviewed-by: Harsh Prateek Bora Signed-off-by: Nicholas Piggin --- target/ppc/cpu.h | 11 +++++++++++ target/ppc/cpu_init.c | 2 +- target/ppc/excp_helper.c | 17 +++++------------ target/ppc/misc_helper.c | 27 ++++++--------------------- target/ppc/timebase_helper.c | 20 +++++++------------- 5 files changed, 30 insertions(+), 47 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 7b52a9bb18..417b284318 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1512,6 +1512,17 @@ struct PowerPCCPUClass { int (*check_attn)(CPUPPCState *env); }; =20 +static inline bool ppc_cpu_core_single_threaded(CPUState *cs) +{ + return cs->nr_threads =3D=3D 1; +} + +static inline bool ppc_cpu_lpar_single_threaded(CPUState *cs) +{ + return !(POWERPC_CPU(cs)->env.flags & POWERPC_FLAG_SMT_1LPAR) || + ppc_cpu_core_single_threaded(cs); +} + ObjectClass *ppc_cpu_class_by_name(const char *name); PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr); PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr); diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 164bb62e63..81dd4e1a7a 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -6993,7 +6993,7 @@ static void ppc_cpu_realize(DeviceState *dev, Error *= *errp) =20 pcc->parent_realize(dev, errp); =20 - if (env_cpu(env)->nr_threads > 1) { + if (!ppc_cpu_core_single_threaded(cs)) { env->flags |=3D POWERPC_FLAG_SMT; } =20 diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 5368bf2ff3..5ecd662f9e 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -3014,18 +3014,11 @@ static void msgsnd_core_tir(CPUPPCState *env, uint3= 2_t target_tir, int irq) { PowerPCCPU *cpu =3D env_archcpu(env); CPUState *cs =3D env_cpu(env); - uint32_t nr_threads =3D cs->nr_threads; =20 - if (!(env->flags & POWERPC_FLAG_SMT_1LPAR)) { - nr_threads =3D 1; /* msgsndp behaves as 1-thread in LPAR-per-threa= d mode*/ - } - - if (target_tir >=3D nr_threads) { - return; - } - - if (nr_threads =3D=3D 1) { - ppc_set_irq(cpu, irq, 1); + if (ppc_cpu_lpar_single_threaded(cs)) { + if (target_tir =3D=3D 0) { + ppc_set_irq(cpu, irq, 1); + } } else { CPUState *ccs; =20 @@ -3080,7 +3073,7 @@ void helper_book3s_msgsnd(CPUPPCState *env, target_ul= ong rb) brdcast =3D true; } =20 - if (cs->nr_threads =3D=3D 1 || !brdcast) { + if (ppc_cpu_core_single_threaded(cs) || !brdcast) { ppc_set_irq(cpu, PPC_INTERRUPT_HDOORBELL, 1); return; } diff --git a/target/ppc/misc_helper.c b/target/ppc/misc_helper.c index 4d3c1bddd9..692e48e6bc 100644 --- a/target/ppc/misc_helper.c +++ b/target/ppc/misc_helper.c @@ -49,9 +49,8 @@ void helper_spr_core_write_generic(CPUPPCState *env, uint= 32_t sprn, { CPUState *cs =3D env_cpu(env); CPUState *ccs; - uint32_t nr_threads =3D cs->nr_threads; =20 - if (nr_threads =3D=3D 1) { + if (ppc_cpu_core_single_threaded(cs)) { env->spr[sprn] =3D val; return; } @@ -196,7 +195,7 @@ void helper_store_ptcr(CPUPPCState *env, target_ulong v= al) return; } =20 - if (cs->nr_threads =3D=3D 1 || !(env->flags & POWERPC_FLAG_SMT_1LP= AR)) { + if (ppc_cpu_lpar_single_threaded(cs)) { env->spr[SPR_PTCR] =3D val; tlb_flush(cs); } else { @@ -243,16 +242,12 @@ target_ulong helper_load_dpdes(CPUPPCState *env) { CPUState *cs =3D env_cpu(env); CPUState *ccs; - uint32_t nr_threads =3D cs->nr_threads; target_ulong dpdes =3D 0; =20 helper_hfscr_facility_check(env, HFSCR_MSGP, "load DPDES", HFSCR_IC_MS= GP); =20 - if (!(env->flags & POWERPC_FLAG_SMT_1LPAR)) { - nr_threads =3D 1; /* DPDES behaves as 1-thread in LPAR-per-thread = mode */ - } - - if (nr_threads =3D=3D 1) { + /* DPDES behaves as 1-thread in LPAR-per-thread mode */ + if (ppc_cpu_lpar_single_threaded(cs)) { if (env->pending_interrupts & PPC_INTERRUPT_DOORBELL) { dpdes =3D 1; } @@ -279,21 +274,11 @@ void helper_store_dpdes(CPUPPCState *env, target_ulon= g val) PowerPCCPU *cpu =3D env_archcpu(env); CPUState *cs =3D env_cpu(env); CPUState *ccs; - uint32_t nr_threads =3D cs->nr_threads; =20 helper_hfscr_facility_check(env, HFSCR_MSGP, "store DPDES", HFSCR_IC_M= SGP); =20 - if (!(env->flags & POWERPC_FLAG_SMT_1LPAR)) { - nr_threads =3D 1; /* DPDES behaves as 1-thread in LPAR-per-thread = mode */ - } - - if (val & ~(nr_threads - 1)) { - qemu_log_mask(LOG_GUEST_ERROR, "Invalid DPDES register value " - TARGET_FMT_lx"\n", val); - val &=3D (nr_threads - 1); /* Ignore the invalid bits */ - } - - if (nr_threads =3D=3D 1) { + /* DPDES behaves as 1-thread in LPAR-per-thread mode */ + if (ppc_cpu_lpar_single_threaded(cs)) { ppc_set_irq(cpu, PPC_INTERRUPT_DOORBELL, val & 0x1); return; } diff --git a/target/ppc/timebase_helper.c b/target/ppc/timebase_helper.c index 52f9e6669c..44cacf065e 100644 --- a/target/ppc/timebase_helper.c +++ b/target/ppc/timebase_helper.c @@ -63,9 +63,8 @@ void helper_store_purr(CPUPPCState *env, target_ulong val) { CPUState *cs =3D env_cpu(env); CPUState *ccs; - uint32_t nr_threads =3D cs->nr_threads; =20 - if (nr_threads =3D=3D 1 || !(env->flags & POWERPC_FLAG_SMT_1LPAR)) { + if (ppc_cpu_lpar_single_threaded(cs)) { cpu_ppc_store_purr(env, val); return; } @@ -82,9 +81,8 @@ void helper_store_tbl(CPUPPCState *env, target_ulong val) { CPUState *cs =3D env_cpu(env); CPUState *ccs; - uint32_t nr_threads =3D cs->nr_threads; =20 - if (nr_threads =3D=3D 1 || !(env->flags & POWERPC_FLAG_SMT_1LPAR)) { + if (ppc_cpu_lpar_single_threaded(cs)) { cpu_ppc_store_tbl(env, val); return; } @@ -99,9 +97,8 @@ void helper_store_tbu(CPUPPCState *env, target_ulong val) { CPUState *cs =3D env_cpu(env); CPUState *ccs; - uint32_t nr_threads =3D cs->nr_threads; =20 - if (nr_threads =3D=3D 1 || !(env->flags & POWERPC_FLAG_SMT_1LPAR)) { + if (ppc_cpu_lpar_single_threaded(cs)) { cpu_ppc_store_tbu(env, val); return; } @@ -141,9 +138,8 @@ void helper_store_hdecr(CPUPPCState *env, target_ulong = val) { CPUState *cs =3D env_cpu(env); CPUState *ccs; - uint32_t nr_threads =3D cs->nr_threads; =20 - if (nr_threads =3D=3D 1 || !(env->flags & POWERPC_FLAG_SMT_1LPAR)) { + if (ppc_cpu_lpar_single_threaded(cs)) { cpu_ppc_store_hdecr(env, val); return; } @@ -158,9 +154,8 @@ void helper_store_vtb(CPUPPCState *env, target_ulong va= l) { CPUState *cs =3D env_cpu(env); CPUState *ccs; - uint32_t nr_threads =3D cs->nr_threads; =20 - if (nr_threads =3D=3D 1 || !(env->flags & POWERPC_FLAG_SMT_1LPAR)) { + if (ppc_cpu_lpar_single_threaded(cs)) { cpu_ppc_store_vtb(env, val); return; } @@ -175,9 +170,8 @@ void helper_store_tbu40(CPUPPCState *env, target_ulong = val) { CPUState *cs =3D env_cpu(env); CPUState *ccs; - uint32_t nr_threads =3D cs->nr_threads; =20 - if (nr_threads =3D=3D 1 || !(env->flags & POWERPC_FLAG_SMT_1LPAR)) { + if (ppc_cpu_lpar_single_threaded(cs)) { cpu_ppc_store_tbu40(env, val); return; } @@ -288,7 +282,7 @@ static void write_tfmr(CPUPPCState *env, target_ulong v= al) { CPUState *cs =3D env_cpu(env); =20 - if (cs->nr_threads =3D=3D 1) { + if (ppc_cpu_core_single_threaded(cs)) { env->spr[SPR_TFMR] =3D val; } else { CPUState *ccs; --=20 2.45.1