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Tue, 16 Jul 2024 09:26:40 -0700 (PDT) From: Nicholas Piggin To: qemu-ppc@nongnu.org Cc: Nicholas Piggin , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20Barrat?= , Harsh Prateek Bora , qemu-devel@nongnu.org Subject: [PATCH v3 04/19] target/ppc: Move SPR indirect registers into PnvCore Date: Wed, 17 Jul 2024 02:26:00 +1000 Message-ID: <20240716162617.32161-5-npiggin@gmail.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240716162617.32161-1-npiggin@gmail.com> References: <20240716162617.32161-1-npiggin@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::c29; envelope-from=npiggin@gmail.com; helo=mail-oo1-xc29.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1721147372831116600 Content-Type: text/plain; charset="utf-8" SPRC/SPRD were recently added to all BookS CPUs supported, but they are only tested on POWER9 and POWER10, so restrict them to those CPUs. SPR indirect scratch registers presently replicated per-CPU like SMT SPRs, but the PnvCore is a better place for them since they are restricted to P9/P10. Also add SPR indirect read access to core thread state for POWER9 since skiboot accesses that when booting to check for big-core mode. Signed-off-by: Nicholas Piggin --- include/hw/ppc/pnv_core.h | 1 + target/ppc/cpu.h | 3 -- target/ppc/cpu_init.c | 21 +++++++------- target/ppc/misc_helper.c | 60 ++++++++++++++++++--------------------- 4 files changed, 39 insertions(+), 46 deletions(-) diff --git a/include/hw/ppc/pnv_core.h b/include/hw/ppc/pnv_core.h index ffec8516ae..693acb189b 100644 --- a/include/hw/ppc/pnv_core.h +++ b/include/hw/ppc/pnv_core.h @@ -53,6 +53,7 @@ struct PnvCore { uint32_t hwid; uint64_t hrmor; =20 + target_ulong scratch[8]; /* SPRC/SPRD indirect SCRATCH registers */ PnvCoreTODState tod_state; =20 PnvChip *chip; diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index c78d6ca91a..95ba9e7590 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1253,9 +1253,6 @@ struct CPUArchState { ppc_slb_t slb[MAX_SLB_ENTRIES]; /* PowerPC 64 SLB area */ struct CPUBreakpoint *ciabr_breakpoint; struct CPUWatchpoint *dawr0_watchpoint; - - /* POWER CPU regs/state */ - target_ulong scratch[8]; /* SCRATCH registers (shared across core) */ #endif target_ulong sr[32]; /* segment registers */ uint32_t nb_BATs; /* number of BATs */ diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index e38f62b08d..164bb62e63 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -5777,16 +5777,6 @@ static void register_power_common_book4_sprs(CPUPPCS= tate *env) SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_core_write_generic, 0x00000000); - spr_register_hv(env, SPR_POWER_SPRC, "SPRC", - SPR_NOACCESS, SPR_NOACCESS, - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_sprc, - 0x00000000); - spr_register_hv(env, SPR_POWER_SPRD, "SPRD", - SPR_NOACCESS, SPR_NOACCESS, - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_sprd, &spr_write_sprd, - 0x00000000); #endif } =20 @@ -5799,6 +5789,17 @@ static void register_power9_book4_sprs(CPUPPCState *= env) SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, KVM_REG_PPC_WORT, 0); + /* SPRC/SPRD exist in earlier CPUs but only tested on POWER9/10 */ + spr_register_hv(env, SPR_POWER_SPRC, "SPRC", + SPR_NOACCESS, SPR_NOACCESS, + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_sprc, + 0x00000000); + spr_register_hv(env, SPR_POWER_SPRD, "SPRD", + SPR_NOACCESS, SPR_NOACCESS, + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_sprd, &spr_write_sprd, + 0x00000000); #endif } =20 diff --git a/target/ppc/misc_helper.c b/target/ppc/misc_helper.c index fa47be2298..4d3c1bddd9 100644 --- a/target/ppc/misc_helper.c +++ b/target/ppc/misc_helper.c @@ -26,6 +26,7 @@ #include "qemu/main-loop.h" #include "mmu-book3s-v3.h" #include "hw/ppc/ppc.h" +#include "hw/ppc/pnv_core.h" =20 #include "helper_regs.h" =20 @@ -321,11 +322,18 @@ void helper_store_sprc(CPUPPCState *env, target_ulong= val) =20 target_ulong helper_load_sprd(CPUPPCState *env) { + /* + * SPRD is a HV-only register for Power CPUs, so this will only be + * accessed by powernv machines. + */ + PowerPCCPU *cpu =3D env_archcpu(env); + PnvCore *pc =3D pnv_cpu_state(cpu)->pnv_core; target_ulong sprc =3D env->spr[SPR_POWER_SPRC]; =20 - switch (sprc & 0x3c0) { - case 0: /* SCRATCH0-7 */ - return env->scratch[(sprc >> 3) & 0x7]; + switch (sprc & 0x3e0) { + case 0: /* SCRATCH0-3 */ + case 1: /* SCRATCH4-7 */ + return pc->scratch[(sprc >> 3) & 0x7]; default: qemu_log_mask(LOG_UNIMP, "mfSPRD: Unimplemented SPRC:0x" TARGET_FMT_lx"\n", sprc); @@ -334,41 +342,27 @@ target_ulong helper_load_sprd(CPUPPCState *env) return 0; } =20 -static void do_store_scratch(CPUPPCState *env, int nr, target_ulong val) -{ - CPUState *cs =3D env_cpu(env); - CPUState *ccs; - uint32_t nr_threads =3D cs->nr_threads; - - /* - * Log stores to SCRATCH, because some firmware uses these for debuggi= ng - * and logging, but they would normally be read by the BMC, which is - * not implemented in QEMU yet. This gives a way to get at the informa= tion. - * Could also dump these upon checkstop. - */ - qemu_log("SPRD write 0x" TARGET_FMT_lx " to SCRATCH%d\n", val, nr); - - if (nr_threads =3D=3D 1) { - env->scratch[nr] =3D val; - return; - } - - THREAD_SIBLING_FOREACH(cs, ccs) { - CPUPPCState *cenv =3D &POWERPC_CPU(ccs)->env; - cenv->scratch[nr] =3D val; - } -} - void helper_store_sprd(CPUPPCState *env, target_ulong val) { target_ulong sprc =3D env->spr[SPR_POWER_SPRC]; - - switch (sprc & 0x3c0) { - case 0: /* SCRATCH0-7 */ - do_store_scratch(env, (sprc >> 3) & 0x7, val); + PowerPCCPU *cpu =3D env_archcpu(env); + PnvCore *pc =3D pnv_cpu_state(cpu)->pnv_core; + + switch (sprc & 0x3e0) { + case 0: /* SCRATCH0-3 */ + case 1: /* SCRATCH4-7 */ + /* + * Log stores to SCRATCH, because some firmware uses these for + * debugging and logging, but they would normally be read by the B= MC, + * which is not implemented in QEMU yet. This gives a way to get a= t the + * information. Could also dump these upon checkstop. + */ + int nr =3D (sprc >> 3) & 0x7; + qemu_log("SPRD write 0x" TARGET_FMT_lx " to SCRATCH%d\n", val, nr); + pc->scratch[nr] =3D val; break; default: - qemu_log_mask(LOG_UNIMP, "mfSPRD: Unimplemented SPRC:0x" + qemu_log_mask(LOG_UNIMP, "mtSPRD: Unimplemented SPRC:0x" TARGET_FMT_lx"\n", sprc); break; } --=20 2.45.1