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Tue, 16 Jul 2024 05:51:03 -0700 (PDT) From: Akihiko Odaki Date: Tue, 16 Jul 2024 21:50:34 +0900 Subject: [PATCH v3 5/5] hvf: arm: Properly disable PMU MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240716-pmu-v3-5-8c7c1858a227@daynix.com> References: <20240716-pmu-v3-0-8c7c1858a227@daynix.com> In-Reply-To: <20240716-pmu-v3-0-8c7c1858a227@daynix.com> To: Peter Maydell , Thomas Huth , Laurent Vivier , Paolo Bonzini Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, kvm@vger.kernel.org, Akihiko Odaki X-Mailer: b4 0.14-dev-fd6e3 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=2607:f8b0:4864:20::62f; envelope-from=akihiko.odaki@daynix.com; helo=mail-pl1-x62f.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @daynix-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1721134317814116600 Setting pmu property used to have no effect for hvf so fix it. Signed-off-by: Akihiko Odaki --- target/arm/hvf/hvf.c | 317 ++++++++++++++++++++++++++---------------------= ---- 1 file changed, 163 insertions(+), 154 deletions(-) diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index eb090e67a2f8..7c593c2d93de 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -1199,57 +1199,23 @@ static bool hvf_sysreg_read_cp(CPUState *cpu, uint3= 2_t reg, uint64_t *val) return false; } =20 -static int hvf_sysreg_read(CPUState *cpu, uint32_t reg, uint32_t rt) +static int hvf_sysreg_read(CPUState *cpu, uint32_t reg, uint32_t rt, + uint64_t *val) { ARMCPU *arm_cpu =3D ARM_CPU(cpu); CPUARMState *env =3D &arm_cpu->env; - uint64_t val =3D 0; =20 switch (reg) { case SYSREG_CNTPCT_EL0: - val =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / - gt_cntfrq_period_ns(arm_cpu); - break; - case SYSREG_PMCR_EL0: - val =3D env->cp15.c9_pmcr; - break; - case SYSREG_PMCCNTR_EL0: - pmu_op_start(env); - val =3D env->cp15.c15_ccnt; - pmu_op_finish(env); - break; - case SYSREG_PMCNTENCLR_EL0: - val =3D env->cp15.c9_pmcnten; - break; - case SYSREG_PMOVSCLR_EL0: - val =3D env->cp15.c9_pmovsr; - break; - case SYSREG_PMSELR_EL0: - val =3D env->cp15.c9_pmselr; - break; - case SYSREG_PMINTENCLR_EL1: - val =3D env->cp15.c9_pminten; - break; - case SYSREG_PMCCFILTR_EL0: - val =3D env->cp15.pmccfiltr_el0; - break; - case SYSREG_PMCNTENSET_EL0: - val =3D env->cp15.c9_pmcnten; - break; - case SYSREG_PMUSERENR_EL0: - val =3D env->cp15.c9_pmuserenr; - break; - case SYSREG_PMCEID0_EL0: - case SYSREG_PMCEID1_EL0: - /* We can't really count anything yet, declare all events invalid = */ - val =3D 0; - break; + *val =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / + gt_cntfrq_period_ns(arm_cpu); + return 0; case SYSREG_OSLSR_EL1: - val =3D env->cp15.oslsr_el1; - break; + *val =3D env->cp15.oslsr_el1; + return 0; case SYSREG_OSDLR_EL1: /* Dummy register */ - break; + return 0; case SYSREG_ICC_AP0R0_EL1: case SYSREG_ICC_AP0R1_EL1: case SYSREG_ICC_AP0R2_EL1: @@ -1276,11 +1242,11 @@ static int hvf_sysreg_read(CPUState *cpu, uint32_t = reg, uint32_t rt) case SYSREG_ICC_SRE_EL1: case SYSREG_ICC_CTLR_EL1: /* Call the TCG sysreg handler. This is only safe for GICv3 regs. = */ - if (!hvf_sysreg_read_cp(cpu, reg, &val)) { + if (!hvf_sysreg_read_cp(cpu, reg, val)) { hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized()); return 1; } - break; + return 0; case SYSREG_DBGBVR0_EL1: case SYSREG_DBGBVR1_EL1: case SYSREG_DBGBVR2_EL1: @@ -1297,8 +1263,8 @@ static int hvf_sysreg_read(CPUState *cpu, uint32_t re= g, uint32_t rt) case SYSREG_DBGBVR13_EL1: case SYSREG_DBGBVR14_EL1: case SYSREG_DBGBVR15_EL1: - val =3D env->cp15.dbgbvr[SYSREG_CRM(reg)]; - break; + *val =3D env->cp15.dbgbvr[SYSREG_CRM(reg)]; + return 0; case SYSREG_DBGBCR0_EL1: case SYSREG_DBGBCR1_EL1: case SYSREG_DBGBCR2_EL1: @@ -1315,8 +1281,8 @@ static int hvf_sysreg_read(CPUState *cpu, uint32_t re= g, uint32_t rt) case SYSREG_DBGBCR13_EL1: case SYSREG_DBGBCR14_EL1: case SYSREG_DBGBCR15_EL1: - val =3D env->cp15.dbgbcr[SYSREG_CRM(reg)]; - break; + *val =3D env->cp15.dbgbcr[SYSREG_CRM(reg)]; + return 0; case SYSREG_DBGWVR0_EL1: case SYSREG_DBGWVR1_EL1: case SYSREG_DBGWVR2_EL1: @@ -1333,8 +1299,8 @@ static int hvf_sysreg_read(CPUState *cpu, uint32_t re= g, uint32_t rt) case SYSREG_DBGWVR13_EL1: case SYSREG_DBGWVR14_EL1: case SYSREG_DBGWVR15_EL1: - val =3D env->cp15.dbgwvr[SYSREG_CRM(reg)]; - break; + *val =3D env->cp15.dbgwvr[SYSREG_CRM(reg)]; + return 0; case SYSREG_DBGWCR0_EL1: case SYSREG_DBGWCR1_EL1: case SYSREG_DBGWCR2_EL1: @@ -1351,35 +1317,64 @@ static int hvf_sysreg_read(CPUState *cpu, uint32_t = reg, uint32_t rt) case SYSREG_DBGWCR13_EL1: case SYSREG_DBGWCR14_EL1: case SYSREG_DBGWCR15_EL1: - val =3D env->cp15.dbgwcr[SYSREG_CRM(reg)]; - break; - default: - if (is_id_sysreg(reg)) { - /* ID system registers read as RES0 */ - val =3D 0; - break; + *val =3D env->cp15.dbgwcr[SYSREG_CRM(reg)]; + return 0; + } + + if (arm_feature(env, ARM_FEATURE_PMU)) { + switch (reg) { + case SYSREG_PMCR_EL0: + *val =3D env->cp15.c9_pmcr; + return 0; + case SYSREG_PMCCNTR_EL0: + pmu_op_start(env); + *val =3D env->cp15.c15_ccnt; + pmu_op_finish(env); + return 0; + case SYSREG_PMCNTENCLR_EL0: + *val =3D env->cp15.c9_pmcnten; + return 0; + case SYSREG_PMOVSCLR_EL0: + *val =3D env->cp15.c9_pmovsr; + return 0; + case SYSREG_PMSELR_EL0: + *val =3D env->cp15.c9_pmselr; + return 0; + case SYSREG_PMINTENCLR_EL1: + *val =3D env->cp15.c9_pminten; + return 0; + case SYSREG_PMCCFILTR_EL0: + *val =3D env->cp15.pmccfiltr_el0; + return 0; + case SYSREG_PMCNTENSET_EL0: + *val =3D env->cp15.c9_pmcnten; + return 0; + case SYSREG_PMUSERENR_EL0: + *val =3D env->cp15.c9_pmuserenr; + return 0; + case SYSREG_PMCEID0_EL0: + case SYSREG_PMCEID1_EL0: + /* We can't really count anything yet, declare all events inva= lid */ + *val =3D 0; + return 0; } - cpu_synchronize_state(cpu); - trace_hvf_unhandled_sysreg_read(env->pc, reg, - SYSREG_OP0(reg), - SYSREG_OP1(reg), - SYSREG_CRN(reg), - SYSREG_CRM(reg), - SYSREG_OP2(reg)); - hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized()); - return 1; - } - - trace_hvf_sysreg_read(reg, - SYSREG_OP0(reg), - SYSREG_OP1(reg), - SYSREG_CRN(reg), - SYSREG_CRM(reg), - SYSREG_OP2(reg), - val); - hvf_set_reg(cpu, rt, val); + } =20 - return 0; + if (is_id_sysreg(reg)) { + /* ID system registers read as RES0 */ + *val =3D 0; + return 0; + } + + cpu_synchronize_state(cpu); + trace_hvf_unhandled_sysreg_read(env->pc, reg, + SYSREG_OP0(reg), + SYSREG_OP1(reg), + SYSREG_CRN(reg), + SYSREG_CRM(reg), + SYSREG_OP2(reg)); + hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized()); + return 1; } =20 static void pmu_update_irq(CPUARMState *env) @@ -1499,69 +1494,12 @@ static int hvf_sysreg_write(CPUState *cpu, uint32_t= reg, uint64_t val) val); =20 switch (reg) { - case SYSREG_PMCCNTR_EL0: - pmu_op_start(env); - env->cp15.c15_ccnt =3D val; - pmu_op_finish(env); - break; - case SYSREG_PMCR_EL0: - pmu_op_start(env); - - if (val & PMCRC) { - /* The counter has been reset */ - env->cp15.c15_ccnt =3D 0; - } - - if (val & PMCRP) { - unsigned int i; - for (i =3D 0; i < pmu_num_counters(env); i++) { - env->cp15.c14_pmevcntr[i] =3D 0; - } - } - - env->cp15.c9_pmcr &=3D ~PMCR_WRITABLE_MASK; - env->cp15.c9_pmcr |=3D (val & PMCR_WRITABLE_MASK); - - pmu_op_finish(env); - break; - case SYSREG_PMUSERENR_EL0: - env->cp15.c9_pmuserenr =3D val & 0xf; - break; - case SYSREG_PMCNTENSET_EL0: - env->cp15.c9_pmcnten |=3D (val & pmu_counter_mask(env)); - break; - case SYSREG_PMCNTENCLR_EL0: - env->cp15.c9_pmcnten &=3D ~(val & pmu_counter_mask(env)); - break; - case SYSREG_PMINTENCLR_EL1: - pmu_op_start(env); - env->cp15.c9_pminten |=3D val; - pmu_op_finish(env); - break; - case SYSREG_PMOVSCLR_EL0: - pmu_op_start(env); - env->cp15.c9_pmovsr &=3D ~val; - pmu_op_finish(env); - break; - case SYSREG_PMSWINC_EL0: - pmu_op_start(env); - pmswinc_write(env, val); - pmu_op_finish(env); - break; - case SYSREG_PMSELR_EL0: - env->cp15.c9_pmselr =3D val & 0x1f; - break; - case SYSREG_PMCCFILTR_EL0: - pmu_op_start(env); - env->cp15.pmccfiltr_el0 =3D val & PMCCFILTR_EL0; - pmu_op_finish(env); - break; case SYSREG_OSLAR_EL1: env->cp15.oslsr_el1 =3D val & 1; - break; + return 0; case SYSREG_OSDLR_EL1: /* Dummy register */ - break; + return 0; case SYSREG_ICC_AP0R0_EL1: case SYSREG_ICC_AP0R1_EL1: case SYSREG_ICC_AP0R2_EL1: @@ -1591,10 +1529,10 @@ static int hvf_sysreg_write(CPUState *cpu, uint32_t= reg, uint64_t val) if (!hvf_sysreg_write_cp(cpu, reg, val)) { hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized()); } - break; + return 0; case SYSREG_MDSCR_EL1: env->cp15.mdscr_el1 =3D val; - break; + return 0; case SYSREG_DBGBVR0_EL1: case SYSREG_DBGBVR1_EL1: case SYSREG_DBGBVR2_EL1: @@ -1612,7 +1550,7 @@ static int hvf_sysreg_write(CPUState *cpu, uint32_t r= eg, uint64_t val) case SYSREG_DBGBVR14_EL1: case SYSREG_DBGBVR15_EL1: env->cp15.dbgbvr[SYSREG_CRM(reg)] =3D val; - break; + return 0; case SYSREG_DBGBCR0_EL1: case SYSREG_DBGBCR1_EL1: case SYSREG_DBGBCR2_EL1: @@ -1630,7 +1568,7 @@ static int hvf_sysreg_write(CPUState *cpu, uint32_t r= eg, uint64_t val) case SYSREG_DBGBCR14_EL1: case SYSREG_DBGBCR15_EL1: env->cp15.dbgbcr[SYSREG_CRM(reg)] =3D val; - break; + return 0; case SYSREG_DBGWVR0_EL1: case SYSREG_DBGWVR1_EL1: case SYSREG_DBGWVR2_EL1: @@ -1648,7 +1586,7 @@ static int hvf_sysreg_write(CPUState *cpu, uint32_t r= eg, uint64_t val) case SYSREG_DBGWVR14_EL1: case SYSREG_DBGWVR15_EL1: env->cp15.dbgwvr[SYSREG_CRM(reg)] =3D val; - break; + return 0; case SYSREG_DBGWCR0_EL1: case SYSREG_DBGWCR1_EL1: case SYSREG_DBGWCR2_EL1: @@ -1666,20 +1604,80 @@ static int hvf_sysreg_write(CPUState *cpu, uint32_t= reg, uint64_t val) case SYSREG_DBGWCR14_EL1: case SYSREG_DBGWCR15_EL1: env->cp15.dbgwcr[SYSREG_CRM(reg)] =3D val; - break; - default: - cpu_synchronize_state(cpu); - trace_hvf_unhandled_sysreg_write(env->pc, reg, - SYSREG_OP0(reg), - SYSREG_OP1(reg), - SYSREG_CRN(reg), - SYSREG_CRM(reg), - SYSREG_OP2(reg)); - hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized()); - return 1; + return 0; } =20 - return 0; + if (arm_feature(env, ARM_FEATURE_PMU)) { + switch (reg) { + case SYSREG_PMCCNTR_EL0: + pmu_op_start(env); + env->cp15.c15_ccnt =3D val; + pmu_op_finish(env); + return 0; + case SYSREG_PMCR_EL0: + pmu_op_start(env); + + if (val & PMCRC) { + /* The counter has been reset */ + env->cp15.c15_ccnt =3D 0; + } + + if (val & PMCRP) { + unsigned int i; + for (i =3D 0; i < pmu_num_counters(env); i++) { + env->cp15.c14_pmevcntr[i] =3D 0; + } + } + + env->cp15.c9_pmcr &=3D ~PMCR_WRITABLE_MASK; + env->cp15.c9_pmcr |=3D (val & PMCR_WRITABLE_MASK); + + pmu_op_finish(env); + return 0; + case SYSREG_PMUSERENR_EL0: + env->cp15.c9_pmuserenr =3D val & 0xf; + return 0; + case SYSREG_PMCNTENSET_EL0: + env->cp15.c9_pmcnten |=3D (val & pmu_counter_mask(env)); + return 0; + case SYSREG_PMCNTENCLR_EL0: + env->cp15.c9_pmcnten &=3D ~(val & pmu_counter_mask(env)); + return 0; + case SYSREG_PMINTENCLR_EL1: + pmu_op_start(env); + env->cp15.c9_pminten |=3D val; + pmu_op_finish(env); + return 0; + case SYSREG_PMOVSCLR_EL0: + pmu_op_start(env); + env->cp15.c9_pmovsr &=3D ~val; + pmu_op_finish(env); + return 0; + case SYSREG_PMSWINC_EL0: + pmu_op_start(env); + pmswinc_write(env, val); + pmu_op_finish(env); + return 0; + case SYSREG_PMSELR_EL0: + env->cp15.c9_pmselr =3D val & 0x1f; + return 0; + case SYSREG_PMCCFILTR_EL0: + pmu_op_start(env); + env->cp15.pmccfiltr_el0 =3D val & PMCCFILTR_EL0; + pmu_op_finish(env); + return 0; + } + } + + cpu_synchronize_state(cpu); + trace_hvf_unhandled_sysreg_write(env->pc, reg, + SYSREG_OP0(reg), + SYSREG_OP1(reg), + SYSREG_CRN(reg), + SYSREG_CRM(reg), + SYSREG_OP2(reg)); + hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized()); + return 1; } =20 static int hvf_inject_interrupts(CPUState *cpu) @@ -1944,7 +1942,18 @@ int hvf_vcpu_exec(CPUState *cpu) int sysreg_ret =3D 0; =20 if (isread) { - sysreg_ret =3D hvf_sysreg_read(cpu, reg, rt); + sysreg_ret =3D hvf_sysreg_read(cpu, reg, rt, &val); + + if (!sysreg_ret) { + trace_hvf_sysreg_read(reg, + SYSREG_OP0(reg), + SYSREG_OP1(reg), + SYSREG_CRN(reg), + SYSREG_CRM(reg), + SYSREG_OP2(reg), + val); + hvf_set_reg(cpu, rt, val); + } } else { val =3D hvf_get_reg(cpu, rt); sysreg_ret =3D hvf_sysreg_write(cpu, reg, val); --=20 2.45.2