From nobody Sat Sep 21 07:33:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1721037538; cv=none; d=zohomail.com; s=zohoarc; b=MFabfMYzi0JDkc44wsw7Gzc1Ms50m1ModrHsbNgCv/NJaentwLJSL4joVycWAGt/OznbGp6WUB+Qd6crspuxRbX0hNS/E/DJX4YXqMzAgyLXXeSfmTh7pResM5EBLpMKI8SJCYd03uQSEB4WbCyp61N5Nk1kHKSfmJkUZlSHAEo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1721037538; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=yXry2MGQMPcGTh+T4VXcwa+K9r3RE5Oob3cP6/p4i/k=; b=O+buhtt20j0IEOOSeirXBHYe7W+g7Kn83x+Wi2Zd/u/D2LYZRF7FZYFqt8Iq+xBnP3wYQPS/H0tKzqT+OQ13C+IUbV07Bj77PkPLmlcv8uWPYx+dRoshWfYVVZ0Mehn7azU2Dm+aXrkZE2qX6gzIINmfWoUxoWoO/uvL0/AEYrg= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1721037538313880.826903117; Mon, 15 Jul 2024 02:58:58 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sTISp-0006Hf-VY; Mon, 15 Jul 2024 05:57:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sTISn-00066N-D1; Mon, 15 Jul 2024 05:57:45 -0400 Received: from 60-248-80-70.hinet-ip.hinet.net ([60.248.80.70] helo=Atcsqr.andestech.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sTISk-00008g-CK; Mon, 15 Jul 2024 05:57:45 -0400 Received: from mail.andestech.com (ATCPCS34.andestech.com [10.0.1.134]) by Atcsqr.andestech.com with ESMTPS id 46F9vE0F072662 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=OK); Mon, 15 Jul 2024 17:57:15 +0800 (+08) (envelope-from ethan84@andestech.com) Received: from atcpcw16.andestech.com (10.0.1.106) by ATCPCS34.andestech.com (10.0.1.134) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Mon, 15 Jul 2024 17:57:16 +0800 To: CC: , , , , , , , , , , , , Ethan Chen Subject: [PATCH v8 1/8] memory: Introduce memory region fetch operation Date: Mon, 15 Jul 2024 17:56:55 +0800 Message-ID: <20240715095702.1222213-2-ethan84@andestech.com> X-Mailer: git-send-email 2.42.0.345.gaab89be2eb.dirty In-Reply-To: <20240715095702.1222213-1-ethan84@andestech.com> References: <20240715095702.1222213-1-ethan84@andestech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.0.1.106] X-ClientProxiedBy: ATCPCS33.andestech.com (10.0.1.100) To ATCPCS34.andestech.com (10.0.1.134) X-DNSRBL: X-SPAM-SOURCE-CHECK: pass X-MAIL: Atcsqr.andestech.com 46F9vE0F072662 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=60.248.80.70; envelope-from=ethan84@andestech.com; helo=Atcsqr.andestech.com X-Spam_score_int: -8 X-Spam_score: -0.9 X-Spam_bar: / X-Spam_report: (-0.9 / 5.0 requ) BAYES_00=-1.9, RDNS_DYNAMIC=0.982, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, TVD_RCVD_IP=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Ethan Chen From: Ethan Chen via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1721037538601116600 Content-Type: text/plain; charset="utf-8" Allow memory regions to have different behaviors for read and fetch operations. For example, the RISC-V IOPMP could raise an interrupt when the CPU tries to fetch from a non-executable region. If the fetch operation for a memory region is not implemented, the read operation will still be used for fetch operations. Signed-off-by: Ethan Chen --- accel/tcg/cputlb.c | 9 +++- include/exec/memory.h | 30 ++++++++++++ system/memory.c | 104 ++++++++++++++++++++++++++++++++++++++++++ system/trace-events | 2 + 4 files changed, 143 insertions(+), 2 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 117b516739..edb3715017 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1942,8 +1942,13 @@ static uint64_t int_ld_mmio_beN(CPUState *cpu, CPUTL= BEntryFull *full, this_size =3D 1 << this_mop; this_mop |=3D MO_BE; =20 - r =3D memory_region_dispatch_read(mr, mr_offset, &val, - this_mop, full->attrs); + if (type =3D=3D MMU_INST_FETCH) { + r =3D memory_region_dispatch_fetch(mr, mr_offset, &val, + this_mop, full->attrs); + } else { + r =3D memory_region_dispatch_read(mr, mr_offset, &val, + this_mop, full->attrs); + } if (unlikely(r !=3D MEMTX_OK)) { io_failed(cpu, full, addr, this_size, type, mmu_idx, r, ra); } diff --git a/include/exec/memory.h b/include/exec/memory.h index 02f7528ec0..d837d7d7eb 100644 --- a/include/exec/memory.h +++ b/include/exec/memory.h @@ -274,6 +274,13 @@ struct MemoryRegionOps { uint64_t data, unsigned size); =20 + /* Fetch from the memory region. @addr is relative to @mr; @size is + * in bytes. */ + uint64_t (*fetch)(void *opaque, + hwaddr addr, + unsigned size); + + MemTxResult (*read_with_attrs)(void *opaque, hwaddr addr, uint64_t *data, @@ -284,6 +291,12 @@ struct MemoryRegionOps { uint64_t data, unsigned size, MemTxAttrs attrs); + MemTxResult (*fetch_with_attrs)(void *opaque, + hwaddr addr, + uint64_t *data, + unsigned size, + MemTxAttrs attrs); + =20 enum device_endian endianness; /* Guest-visible constraints: */ @@ -2602,6 +2615,23 @@ MemTxResult memory_region_dispatch_write(MemoryRegio= n *mr, MemOp op, MemTxAttrs attrs); =20 + +/** + * memory_region_dispatch_fetch: perform a fetch directly to the specified + * MemoryRegion. + * + * @mr: #MemoryRegion to access + * @addr: address within that region + * @pval: pointer to uint64_t which the data is written to + * @op: size, sign, and endianness of the memory operation + * @attrs: memory transaction attributes to use for the access + */ +MemTxResult memory_region_dispatch_fetch(MemoryRegion *mr, + hwaddr addr, + uint64_t *pval, + MemOp op, + MemTxAttrs attrs); + /** * address_space_init: initializes an address space * diff --git a/system/memory.c b/system/memory.c index 5e6eb459d5..b46721446c 100644 --- a/system/memory.c +++ b/system/memory.c @@ -477,6 +477,51 @@ static MemTxResult memory_region_read_with_attrs_acces= sor(MemoryRegion *mr, return r; } =20 +static MemTxResult memory_region_fetch_accessor(MemoryRegion *mr, + hwaddr addr, + uint64_t *value, + unsigned size, + signed shift, + uint64_t mask, + MemTxAttrs attrs) +{ + uint64_t tmp; + + tmp =3D mr->ops->fetch(mr->opaque, addr, size); + if (mr->subpage) { + trace_memory_region_subpage_fetch(get_cpu_index(), mr, addr, tmp, = size); + } else if (trace_event_get_state_backends(TRACE_MEMORY_REGION_OPS_FETC= H)) { + hwaddr abs_addr =3D memory_region_to_absolute_addr(mr, addr); + trace_memory_region_ops_fetch(get_cpu_index(), mr, abs_addr, tmp, = size, + memory_region_name(mr)); + } + memory_region_shift_read_access(value, shift, mask, tmp); + return MEMTX_OK; +} + +static MemTxResult memory_region_fetch_with_attrs_accessor(MemoryRegion *m= r, + hwaddr addr, + uint64_t *value, + unsigned size, + signed shift, + uint64_t mask, + MemTxAttrs attrs) +{ + uint64_t tmp =3D 0; + MemTxResult r; + + r =3D mr->ops->fetch_with_attrs(mr->opaque, addr, &tmp, size, attrs); + if (mr->subpage) { + trace_memory_region_subpage_fetch(get_cpu_index(), mr, addr, tmp, = size); + } else if (trace_event_get_state_backends(TRACE_MEMORY_REGION_OPS_FETC= H)) { + hwaddr abs_addr =3D memory_region_to_absolute_addr(mr, addr); + trace_memory_region_ops_fetch(get_cpu_index(), mr, abs_addr, tmp, = size, + memory_region_name(mr)); + } + memory_region_shift_read_access(value, shift, mask, tmp); + return r; +} + static MemTxResult memory_region_write_accessor(MemoryRegion *mr, hwaddr addr, uint64_t *value, @@ -1461,6 +1506,65 @@ MemTxResult memory_region_dispatch_read(MemoryRegion= *mr, return r; } =20 +static MemTxResult memory_region_dispatch_fetch1(MemoryRegion *mr, + hwaddr addr, + uint64_t *pval, + unsigned size, + MemTxAttrs attrs) +{ + *pval =3D 0; + + if (mr->ops->fetch) { + return access_with_adjusted_size(addr, pval, size, + mr->ops->impl.min_access_size, + mr->ops->impl.max_access_size, + memory_region_fetch_accessor, + mr, attrs); + } else if (mr->ops->fetch_with_attrs) { + return access_with_adjusted_size(addr, pval, size, + mr->ops->impl.min_access_size, + mr->ops->impl.max_access_size, + memory_region_fetch_with_attrs_accessor, + mr, attrs); + } else if (mr->ops->read) { + return access_with_adjusted_size(addr, pval, size, + mr->ops->impl.min_access_size, + mr->ops->impl.max_access_size, + memory_region_read_accessor, + mr, attrs); + } else { + return access_with_adjusted_size(addr, pval, size, + mr->ops->impl.min_access_size, + mr->ops->impl.max_access_size, + memory_region_read_with_attrs_acc= essor, + mr, attrs); + } +} + +MemTxResult memory_region_dispatch_fetch(MemoryRegion *mr, + hwaddr addr, + uint64_t *pval, + MemOp op, + MemTxAttrs attrs) +{ + unsigned size =3D memop_size(op); + MemTxResult r; + + if (mr->alias) { + return memory_region_dispatch_fetch(mr->alias, + mr->alias_offset + addr, + pval, op, attrs); + } + if (!memory_region_access_valid(mr, addr, size, false, attrs)) { + *pval =3D unassigned_mem_read(mr, addr, size); + return MEMTX_DECODE_ERROR; + } + + r =3D memory_region_dispatch_fetch1(mr, addr, pval, size, attrs); + adjust_endianness(mr, pval, op); + return r; +} + /* Return true if an eventfd was signalled */ static bool memory_region_dispatch_write_eventfds(MemoryRegion *mr, hwaddr addr, diff --git a/system/trace-events b/system/trace-events index 2ed1d59b1f..a8fc70f28f 100644 --- a/system/trace-events +++ b/system/trace-events @@ -11,8 +11,10 @@ cpu_out(unsigned int addr, char size, unsigned int val) = "addr 0x%x(%c) value %u" # memory.c memory_region_ops_read(int cpu_index, void *mr, uint64_t addr, uint64_t va= lue, unsigned size, const char *name) "cpu %d mr %p addr 0x%"PRIx64" value = 0x%"PRIx64" size %u name '%s'" memory_region_ops_write(int cpu_index, void *mr, uint64_t addr, uint64_t v= alue, unsigned size, const char *name) "cpu %d mr %p addr 0x%"PRIx64" value= 0x%"PRIx64" size %u name '%s'" +memory_region_ops_fetch(int cpu_index, void *mr, uint64_t addr, uint64_t v= alue, unsigned size, const char *name) "cpu %d mr %p addr 0x%"PRIx64" value= 0x%"PRIx64" size %u name '%s'" memory_region_subpage_read(int cpu_index, void *mr, uint64_t offset, uint6= 4_t value, unsigned size) "cpu %d mr %p offset 0x%"PRIx64" value 0x%"PRIx64= " size %u" memory_region_subpage_write(int cpu_index, void *mr, uint64_t offset, uint= 64_t value, unsigned size) "cpu %d mr %p offset 0x%"PRIx64" value 0x%"PRIx6= 4" size %u" +memory_region_subpage_fetch(int cpu_index, void *mr, uint64_t offset, uint= 64_t value, unsigned size) "cpu %d mr %p offset 0x%"PRIx64" value 0x%"PRIx6= 4" size %u" memory_region_ram_device_read(int cpu_index, void *mr, uint64_t addr, uint= 64_t value, unsigned size) "cpu %d mr %p addr 0x%"PRIx64" value 0x%"PRIx64"= size %u" memory_region_ram_device_write(int cpu_index, void *mr, uint64_t addr, uin= t64_t value, unsigned size) "cpu %d mr %p addr 0x%"PRIx64" value 0x%"PRIx64= " size %u" memory_region_sync_dirty(const char *mr, const char *listener, int global)= "mr '%s' listener '%s' synced (global=3D%d)" --=20 2.34.1