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Henry" , Richard Henderson Subject: [PULL 08/13] target/i386/tcg: Use DPL-level accesses for interrupts and call gates Date: Sun, 14 Jul 2024 13:10:38 +0200 Message-ID: <20240714111043.14132-9-pbonzini@redhat.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240714111043.14132-1-pbonzini@redhat.com> References: <20240714111043.14132-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=-0.01, RCVD_IN_MSPIKE_WL=-0.01, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1720955597460116600 Content-Type: text/plain; charset="utf-8" This fixes a bug wherein i386/tcg assumed an interrupt return using the CALL or JMP instructions were always going from kernel or user mode to kernel mode, when using a call gate. This assumption is violated if the call gate has a DPL that is greater than 0. In addition, the stack accesses should count as explicit, not implicit ("kernel" in QEMU code), so that SMAP is not applied if DPL=3D3. Analyzed-by: Robert R. Henry Resolves: https://gitlab.com/qemu-project/qemu/-/issues/249 Reviewed-by: Richard Henderson Signed-off-by: Paolo Bonzini --- target/i386/tcg/seg_helper.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/target/i386/tcg/seg_helper.c b/target/i386/tcg/seg_helper.c index 8a6d92b3583..809ee3d9833 100644 --- a/target/i386/tcg/seg_helper.c +++ b/target/i386/tcg/seg_helper.c @@ -678,7 +678,7 @@ static void do_interrupt_protected(CPUX86State *env, in= t intno, int is_int, =20 sa.env =3D env; sa.ra =3D 0; - sa.mmu_index =3D cpu_mmu_index_kernel(env); + sa.mmu_index =3D x86_mmu_index_pl(env, dpl); =20 if (type =3D=3D 5) { /* task gate */ @@ -984,7 +984,7 @@ static void do_interrupt64(CPUX86State *env, int intno,= int is_int, =20 sa.env =3D env; sa.ra =3D 0; - sa.mmu_index =3D cpu_mmu_index_kernel(env); + sa.mmu_index =3D x86_mmu_index_pl(env, dpl); sa.sp_mask =3D -1; sa.ss_base =3D 0; if (dpl < cpl || ist !=3D 0) { @@ -1119,7 +1119,7 @@ static void do_interrupt_real(CPUX86State *env, int i= ntno, int is_int, sa.sp =3D env->regs[R_ESP]; sa.sp_mask =3D 0xffff; sa.ss_base =3D env->segs[R_SS].base; - sa.mmu_index =3D cpu_mmu_index_kernel(env); + sa.mmu_index =3D x86_mmu_index_pl(env, 0); =20 if (is_int) { old_eip =3D next_eip; @@ -1583,7 +1583,7 @@ void helper_lcall_real(CPUX86State *env, uint32_t new= _cs, uint32_t new_eip, sa.sp =3D env->regs[R_ESP]; sa.sp_mask =3D get_sp_mask(env->segs[R_SS].flags); sa.ss_base =3D env->segs[R_SS].base; - sa.mmu_index =3D cpu_mmu_index_kernel(env); + sa.mmu_index =3D x86_mmu_index_pl(env, 0); =20 if (shift) { pushl(&sa, env->segs[R_CS].selector); @@ -1619,17 +1619,17 @@ void helper_lcall_protected(CPUX86State *env, int n= ew_cs, target_ulong new_eip, raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc, GETPC()); } cpl =3D env->hflags & HF_CPL_MASK; + dpl =3D (e2 >> DESC_DPL_SHIFT) & 3; LOG_PCALL("desc=3D%08x:%08x\n", e1, e2); =20 sa.env =3D env; sa.ra =3D GETPC(); - sa.mmu_index =3D cpu_mmu_index_kernel(env); + sa.mmu_index =3D x86_mmu_index_pl(env, dpl); =20 if (e2 & DESC_S_MASK) { if (!(e2 & DESC_CS_MASK)) { raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc, GETPC= ()); } - dpl =3D (e2 >> DESC_DPL_SHIFT) & 3; if (e2 & DESC_C_MASK) { /* conforming code segment */ if (dpl > cpl) { @@ -1691,7 +1691,6 @@ void helper_lcall_protected(CPUX86State *env, int new= _cs, target_ulong new_eip, } else { /* check gate type */ type =3D (e2 >> DESC_TYPE_SHIFT) & 0x1f; - dpl =3D (e2 >> DESC_DPL_SHIFT) & 3; rpl =3D new_cs & 3; =20 #ifdef TARGET_X86_64 --=20 2.45.2