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Fri, 12 Jul 2024 05:04:25 -0700 (PDT) From: Nicholas Piggin To: qemu-ppc@nongnu.org Cc: Nicholas Piggin , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20Barrat?= , Harsh Prateek Bora , qemu-devel@nongnu.org Subject: [PATCH v2 14/19] ppc/pnv: Add POWER10 ChipTOD quirk for big-core Date: Fri, 12 Jul 2024 22:02:41 +1000 Message-ID: <20240712120247.477133-15-npiggin@gmail.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240712120247.477133-1-npiggin@gmail.com> References: <20240712120247.477133-1-npiggin@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=npiggin@gmail.com; helo=mail-pf1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1720786007028116600 Content-Type: text/plain; charset="utf-8" POWER10 has a quirk in its ChipTOD addressing that requires the even small-core to be selected even when programming the odd small-core. This allows skiboot chiptod init to run in big-core mode. Signed-off-by: Nicholas Piggin --- include/hw/ppc/pnv.h | 1 + include/hw/ppc/pnv_core.h | 7 +++++++ hw/ppc/pnv.c | 7 ++++++- target/ppc/timebase_helper.c | 9 +++++++++ 4 files changed, 23 insertions(+), 1 deletion(-) diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index 283ddd50e7..c56d152889 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -77,6 +77,7 @@ struct PnvMachineClass { const char *compat; int compat_size; int max_smt_threads; + bool quirk_tb_big_core; =20 void (*dt_power_mgt)(PnvMachineState *pnv, void *fdt); void (*i2c_init)(PnvMachineState *pnv); diff --git a/include/hw/ppc/pnv_core.h b/include/hw/ppc/pnv_core.h index 50164e9e1f..c8784777a4 100644 --- a/include/hw/ppc/pnv_core.h +++ b/include/hw/ppc/pnv_core.h @@ -27,6 +27,13 @@ =20 /* Per-core ChipTOD / TimeBase state */ typedef struct PnvCoreTODState { + /* + * POWER10 DD2.0 - big core TFMR drives the state machine on the even + * small core. Skiboot has a workaround that targets the even small co= re + * for CHIPTOD_TO_TB ops. + */ + bool big_core_quirk; + int tb_ready_for_tod; /* core TB ready to receive TOD from chiptod */ int tod_sent_to_tb; /* chiptod sent TOD to the core TB */ =20 diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index fdf66323b8..24f7c007ce 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -2288,11 +2288,12 @@ static void pnv_chip_core_sanitize(PnvMachineState = *pnv, PnvChip *chip, =20 static void pnv_chip_core_realize(PnvChip *chip, Error **errp) { + PnvMachineState *pnv =3D PNV_MACHINE(qdev_get_machine()); + PnvMachineClass *pmc =3D PNV_MACHINE_GET_CLASS(pnv); Error *error =3D NULL; PnvChipClass *pcc =3D PNV_CHIP_GET_CLASS(chip); const char *typename =3D pnv_chip_core_typename(chip); int i, core_hwid; - PnvMachineState *pnv =3D PNV_MACHINE(qdev_get_machine()); =20 if (!object_class_by_name(typename)) { error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typename); @@ -2335,6 +2336,9 @@ static void pnv_chip_core_realize(PnvChip *chip, Erro= r **errp) &error_fatal); object_property_set_link(OBJECT(pnv_core), "chip", OBJECT(chip), &error_abort); + + pnv_core->tod_state.big_core_quirk =3D pmc->quirk_tb_big_core; + qdev_realize(DEVICE(pnv_core), NULL, &error_fatal); =20 /* Each core has an XSCOM MMIO region */ @@ -2647,6 +2651,7 @@ static void pnv_machine_p10_common_class_init(ObjectC= lass *oc, void *data) pmc->compat =3D compat; pmc->compat_size =3D sizeof(compat); pmc->max_smt_threads =3D 4; + pmc->quirk_tb_big_core =3D true; pmc->dt_power_mgt =3D pnv_dt_power_mgt; =20 xfc->match_nvt =3D pnv10_xive_match_nvt; diff --git a/target/ppc/timebase_helper.c b/target/ppc/timebase_helper.c index 44cacf065e..019b8ee41f 100644 --- a/target/ppc/timebase_helper.c +++ b/target/ppc/timebase_helper.c @@ -20,6 +20,7 @@ #include "cpu.h" #include "hw/ppc/ppc.h" #include "hw/ppc/pnv_core.h" +#include "hw/ppc/pnv_chip.h" #include "exec/helper-proto.h" #include "exec/exec-all.h" #include "qemu/log.h" @@ -297,6 +298,14 @@ static PnvCoreTODState *cpu_get_tbst(PowerPCCPU *cpu) { PnvCore *pc =3D pnv_cpu_state(cpu)->pnv_core; =20 + if (pc->big_core && pc->tod_state.big_core_quirk) { + /* Must operate on the even small core */ + int core_id =3D CPU_CORE(pc)->core_id; + if (core_id & 1) { + pc =3D pc->chip->cores[core_id & ~1]; + } + } + return &pc->tod_state; } =20 --=20 2.45.1