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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4279f23999csm21271065e9.8.2024.07.12.04.39.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 12 Jul 2024 04:39:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1720784392; x=1721389192; darn=nongnu.org; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=Qzrqy4xZtYfOCZcOV4JdoM5syuVE4DAO9tvUdp9cVHA=; b=w0slXDEpXU6/yHnnFD9Ae34I7kRZ9rUcNlwLder9gokw2NwnJoMzYg2JjtLNrxI3qW elQnAqDr5ct/OiG96Z7sW0PkSRWhssqGo7w/S2Tb6D4IlXSgxF+bX44nIQqdDK8UF72H ROHo8V+us08uyKaPO0+gyhFPh3I4UMXRdbp4Jy5RY4rhgS2FoNHuO57bhkq0DpjStHnQ jsJhg5nBhWJLdZKdHhWPTh1NkZMO+q3b67nrZCZqPT7sgsGxCqW9MLwj0bhfGieQZIRL LhiXFzxDIFTXreRarSuhl448DJQa3hygzqkgmHdoRYu9mI7s6WUxjo70TpaHdKNvJHrQ QFPw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1720784392; x=1721389192; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=Qzrqy4xZtYfOCZcOV4JdoM5syuVE4DAO9tvUdp9cVHA=; b=iz3qKw/0w8PnYJ2zBpLQwTZ5A02yaXMaWJAeB61Us9Rm5icQsxPRgxdp7fLyQExpEc O3Se/7MfcWsVE3/v8a9hIknnz+720IiDmrPs3lZXvRhz6hpWEGJFDSstcdQVnxiqAWgb Asqovr8g4pchm6Ps9rFg4u8Dc4SY0W2QjPiOMWcwl5rSe38YvFa0sv/9l2h4XKfx/per KckL3McoWNH7aTRjiZoBmdTmdK4ZH7SvW2zBrSdY6VTP37xLEnf4jdNDgztCftkdOn+r 6VEgGrDLhPPSj6dtV9tayuNqWHhKSS1TBEQTjBWTW/83rMP2qFB6O52SgC79Moqslirc /jAA== X-Gm-Message-State: AOJu0YzZowLVa+dJ+0vMbhjdzC/Vg0hYV16fU3qJiLBvXN4lg6qrhVLW t/RQp5DWmeiyt0Q/LJ8Lhjrqa06TgqpoawACCSJ1quTy5x7cmMgfUU2hsd+SNtyInItijrqUw8b LlGo= X-Google-Smtp-Source: AGHT+IGpqoYbfIXqjJNI9xo7Z/buUB7yPUmn8JVqr0vMBp5ioTwY6+MJMn59oTngs6NUpYz19jsGfw== X-Received: by 2002:a05:600c:5748:b0:426:597c:7d58 with SMTP id 5b1f17b1804b1-426708fabf5mr70773865e9.39.1720784392160; Fri, 12 Jul 2024 04:39:52 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Cc: Richard Henderson , Bastian Koppelmann Subject: [PATCH] accel/tcg: Make cpu_exec_interrupt hook mandatory Date: Fri, 12 Jul 2024 12:39:49 +0100 Message-Id: <20240712113949.4146855-1-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1720784465729116600 Content-Type: text/plain; charset="utf-8" The TCGCPUOps::cpu_exec_interrupt hook is currently not mandatory; if it is left NULL then we treat it as if it had returned false. However since pretty much every architecture needs to handle interrupts, almost every target we have provides the hook. The one exception is Tricore, which doesn't currently implement the architectural interrupt handling. Add a "do nothing" implementation of cpu_exec_hook for Tricore, assert on startup that the CPU does provide the hook, and remove the runtime NULL check before calling it. Signed-off-by: Peter Maydell Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- accel/tcg/cpu-exec.c | 4 ++-- target/tricore/cpu.c | 6 ++++++ 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 245fd6327da..9010dad0738 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -857,8 +857,7 @@ static inline bool cpu_handle_interrupt(CPUState *cpu, else { const TCGCPUOps *tcg_ops =3D cpu->cc->tcg_ops; =20 - if (tcg_ops->cpu_exec_interrupt && - tcg_ops->cpu_exec_interrupt(cpu, interrupt_request)) { + if (tcg_ops->cpu_exec_interrupt(cpu, interrupt_request)) { if (!tcg_ops->need_replay_interrupt || tcg_ops->need_replay_interrupt(interrupt_request)) { replay_interrupt(); @@ -1080,6 +1079,7 @@ bool tcg_exec_realizefn(CPUState *cpu, Error **errp) /* Check mandatory TCGCPUOps handlers */ #ifndef CONFIG_USER_ONLY assert(cpu->cc->tcg_ops->cpu_exec_halt); + assert(cpu->cc->tcg_ops->cpu_exec_interrupt); #endif /* !CONFIG_USER_ONLY */ cpu->cc->tcg_ops->initialize(); tcg_target_initialized =3D true; diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index 4d9c0368f2b..1a261715907 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -155,6 +155,11 @@ static void tc37x_initfn(Object *obj) set_feature(&cpu->env, TRICORE_FEATURE_162); } =20 +static bool tricore_cpu_exec_interrupt(CPUState *cs, int interrupt_request) +{ + /* Interrupts are not implemented */ + return false; +} =20 #include "hw/core/sysemu-cpu-ops.h" =20 @@ -169,6 +174,7 @@ static const TCGCPUOps tricore_tcg_ops =3D { .synchronize_from_tb =3D tricore_cpu_synchronize_from_tb, .restore_state_to_opc =3D tricore_restore_state_to_opc, .tlb_fill =3D tricore_cpu_tlb_fill, + .cpu_exec_interrupt =3D tricore_cpu_exec_interrupt, .cpu_exec_halt =3D tricore_cpu_has_work, }; =20 --=20 2.34.1