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a=openpgp-sha256; l=3605; i=k.jensen@samsung.com; h=from:subject; bh=ywvt19DaycrPLQkuZuEEUyxvLK5gVPKhT1LHVJGcO7E=; b=owJ4nAFtAZL+kA0DAAoBTeGvMW1PDekByyZiAGaQHrVsA41B5SgfmIxk0DTZY68fp1c4Y3W9B sGFKD/4N86spIkBMwQAAQoAHRYhBFIoM6p14tzmokdmwE3hrzFtTw3pBQJmkB61AAoJEE3hrzFt Tw3pOyEH/1zYW5Xl9xW2BWdhcZruugVIjhwj848zZ1vGdF0wItcCE1FIu8wM2WarG0dhGmly0Pp loo1nYrQPr3kKYMl8SKLsIEup2V+pntajoV11oeArKUaNA2wv8X4YUdouvjTgXmiXfJronHMi6W wH8goCoPdGfX8S61y4AXhJMUJIUOh3RSIOxPMeYDvgyTvzfVvmusbi7sh2fX1LO1MbrMddPbvaJ vDg3/R7yQaLVD3c9iYTBJ38NWJX2OLQjdmJhie5aEVgALtI8y7/aiNJMQ3g4VYumUI77/3qRnMw ICRHq+0LwljIC8yvJQXQj5vIq1iceFeYuWd1UZolCETkjioP+JsI1qSl X-Developer-Key: i=k.jensen@samsung.com; a=openpgp; fpr=DDCA4D9C9EF931CC3468427263D56FC5E55DA838 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=103.168.172.156; envelope-from=its@irrelevant.dk; helo=fhigh5-smtp.messagingengine.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @irrelevant.dk) X-ZM-MESSAGEID: 1720721179368116600 Content-Type: text/plain; charset="utf-8" From: Minwoo Im PF initializes SR-IOV VF BAR0 region in nvme_init_sriov() with bar_size calcaulted by Primary Controller Capability such as VQFRSM and VIFRSM rather than `max_ioqpairs` and `msix_qsize` which is for PF only. In this case, the bar size reported in nvme_init_sriov() by PF and nvme_init_pci() by VF might differ especially with large number of sriov_max_vfs (e.g., 127 which is curret maximum number of VFs). And this reports invalid BAR0 address of VFs to the host operating system so that MMIO access will not be caught properly and, of course, NVMe driver initialization is failed. For example, if we give the following options, BAR size will be initialized by PF with 4K, but VF will try to allocate 8K BAR0 size in nvme_init_pci(). #!/bin/bash nr_vf=3D$((127)) nr_vq=3D$(($nr_vf * 2 + 2)) nr_vi=3D$(($nr_vq / 2 + 1)) nr_ioq=3D$(($nr_vq + 2)) ... -device nvme,serial=3Dfoo,id=3Dnvme0,bus=3Drp2,subsys=3Dsubsys0,mdts=3D9,m= six_qsize=3D$nr_ioq,max_ioqpairs=3D$nr_ioq,sriov_max_vfs=3D$nr_vf,sriov_vq_= flexible=3D$nr_vq,sriov_vi_flexible=3D$nr_vi \ To fix this issue, this patch modifies the calculation of BAR size in the PF and VF initialization by using different elements: PF: `max_ioqpairs + 1` with `msix_qsize` VF: VQFRSM with VIFRSM Signed-off-by: Minwoo Im Reviewed-by: Klaus Jensen Signed-off-by: Klaus Jensen --- hw/nvme/ctrl.c | 19 +++++++++++++++---- 1 file changed, 15 insertions(+), 4 deletions(-) diff --git a/hw/nvme/ctrl.c b/hw/nvme/ctrl.c index 231e1127cec8..f3ae54896f6d 100644 --- a/hw/nvme/ctrl.c +++ b/hw/nvme/ctrl.c @@ -8104,6 +8104,7 @@ static bool nvme_init_pci(NvmeCtrl *n, PCIDevice *pci= _dev, Error **errp) uint8_t *pci_conf =3D pci_dev->config; uint64_t bar_size; unsigned msix_table_offset =3D 0, msix_pba_offset =3D 0; + unsigned nr_vectors; int ret; =20 pci_conf[PCI_INTERRUPT_PIN] =3D 1; @@ -8136,9 +8137,19 @@ static bool nvme_init_pci(NvmeCtrl *n, PCIDevice *pc= i_dev, Error **errp) assert(n->params.msix_qsize >=3D 1); =20 /* add one to max_ioqpairs to account for the admin queue pair */ - bar_size =3D nvme_mbar_size(n->params.max_ioqpairs + 1, - n->params.msix_qsize, &msix_table_offset, - &msix_pba_offset); + if (!pci_is_vf(pci_dev)) { + nr_vectors =3D n->params.msix_qsize; + bar_size =3D nvme_mbar_size(n->params.max_ioqpairs + 1, + nr_vectors, &msix_table_offset, + &msix_pba_offset); + } else { + NvmeCtrl *pn =3D NVME(pcie_sriov_get_pf(pci_dev)); + NvmePriCtrlCap *cap =3D &pn->pri_ctrl_cap; + + nr_vectors =3D le16_to_cpu(cap->vifrsm); + bar_size =3D nvme_mbar_size(le16_to_cpu(cap->vqfrsm), nr_vecto= rs, + &msix_table_offset, &msix_pba_offset= ); + } =20 memory_region_init(&n->bar0, OBJECT(n), "nvme-bar0", bar_size); memory_region_init_io(&n->iomem, OBJECT(n), &nvme_mmio_ops, n, "nv= me", @@ -8152,7 +8163,7 @@ static bool nvme_init_pci(NvmeCtrl *n, PCIDevice *pci= _dev, Error **errp) PCI_BASE_ADDRESS_MEM_TYPE_64, &n->bar0); } =20 - ret =3D msix_init(pci_dev, n->params.msix_qsize, + ret =3D msix_init(pci_dev, nr_vectors, &n->bar0, 0, msix_table_offset, &n->bar0, 0, msix_pba_offset, 0, errp); } --=20 2.44.0