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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::22d; envelope-from=peter.maydell@linaro.org; helo=mail-lj1-x22d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1720704146062116600 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20240709000610.382391-6-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/a64.decode | 5 ++ target/arm/tcg/translate-a64.c | 127 +++++++++++++++------------------ 2 files changed, 61 insertions(+), 71 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index 32e2f3a0d55..afb34a8fd43 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -998,6 +998,11 @@ UADDW 0.10 1110 ..1 ..... 00010 0 ..... ....= . @qrrr_e SSUBW 0.00 1110 ..1 ..... 00110 0 ..... ..... @qrrr_e USUBW 0.10 1110 ..1 ..... 00110 0 ..... ..... @qrrr_e =20 +ADDHN 0.00 1110 ..1 ..... 01000 0 ..... ..... @qrrr_e +RADDHN 0.10 1110 ..1 ..... 01000 0 ..... ..... @qrrr_e +SUBHN 0.00 1110 ..1 ..... 01100 0 ..... ..... @qrrr_e +RSUBHN 0.10 1110 ..1 ..... 01100 0 ..... ..... @qrrr_e + ### Advanced SIMD scalar x indexed element =20 FMUL_si 0101 1111 00 .. .... 1001 . 0 ..... ..... @rrx_h diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 264d2eeb27d..3e0dacdd63c 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -5949,6 +5949,60 @@ TRANS(UADDW, do_addsub_wide, a, 0, false) TRANS(SSUBW, do_addsub_wide, a, MO_SIGN, true) TRANS(USUBW, do_addsub_wide, a, 0, true) =20 +static bool do_addsub_highnarrow(DisasContext *s, arg_qrrr_e *a, + bool sub, bool round) +{ + TCGv_i64 tcg_op0, tcg_op1; + MemOp esz =3D a->esz; + int half =3D 8 >> esz; + bool top =3D a->q; + int ebits =3D 8 << esz; + uint64_t rbit =3D 1ull << (ebits - 1); + int top_swap, top_half; + + /* There are no 128x128->64 bit operations. */ + if (esz >=3D MO_64) { + return false; + } + if (!fp_access_check(s)) { + return true; + } + tcg_op0 =3D tcg_temp_new_i64(); + tcg_op1 =3D tcg_temp_new_i64(); + + /* + * For top half inputs, iterate backward; forward for bottom half. + * This means the store to the destination will not occur until + * overlapping input inputs are consumed. + */ + top_swap =3D top ? half - 1 : 0; + top_half =3D top ? half : 0; + + for (int elt_fwd =3D 0; elt_fwd < half; ++elt_fwd) { + int elt =3D elt_fwd ^ top_swap; + + read_vec_element(s, tcg_op1, a->rm, elt, esz + 1); + read_vec_element(s, tcg_op0, a->rn, elt, esz + 1); + if (sub) { + tcg_gen_sub_i64(tcg_op0, tcg_op0, tcg_op1); + } else { + tcg_gen_add_i64(tcg_op0, tcg_op0, tcg_op1); + } + if (round) { + tcg_gen_addi_i64(tcg_op0, tcg_op0, rbit); + } + tcg_gen_shri_i64(tcg_op0, tcg_op0, ebits); + write_vec_element(s, tcg_op0, a->rd, elt + top_half, esz); + } + clear_vec_high(s, top, a->rd); + return true; +} + +TRANS(ADDHN, do_addsub_highnarrow, a, false, false) +TRANS(SUBHN, do_addsub_highnarrow, a, true, false) +TRANS(RADDHN, do_addsub_highnarrow, a, false, true) +TRANS(RSUBHN, do_addsub_highnarrow, a, true, true) + /* * Advanced SIMD scalar/vector x indexed element */ @@ -10813,65 +10867,6 @@ static void disas_simd_shift_imm(DisasContext *s, = uint32_t insn) } } =20 -/* Generate code to do a "long" addition or subtraction, ie one done in - * TCGv_i64 on vector lanes twice the width specified by size. - */ -static void gen_neon_addl(int size, bool is_sub, TCGv_i64 tcg_res, - TCGv_i64 tcg_op1, TCGv_i64 tcg_op2) -{ - static NeonGenTwo64OpFn * const fns[3][2] =3D { - { gen_helper_neon_addl_u16, gen_helper_neon_subl_u16 }, - { gen_helper_neon_addl_u32, gen_helper_neon_subl_u32 }, - { tcg_gen_add_i64, tcg_gen_sub_i64 }, - }; - NeonGenTwo64OpFn *genfn; - assert(size < 3); - - genfn =3D fns[size][is_sub]; - genfn(tcg_res, tcg_op1, tcg_op2); -} - -static void do_narrow_round_high_u32(TCGv_i32 res, TCGv_i64 in) -{ - tcg_gen_addi_i64(in, in, 1U << 31); - tcg_gen_extrh_i64_i32(res, in); -} - -static void handle_3rd_narrowing(DisasContext *s, int is_q, int is_u, int = size, - int opcode, int rd, int rn, int rm) -{ - TCGv_i32 tcg_res[2]; - int part =3D is_q ? 2 : 0; - int pass; - - for (pass =3D 0; pass < 2; pass++) { - TCGv_i64 tcg_op1 =3D tcg_temp_new_i64(); - TCGv_i64 tcg_op2 =3D tcg_temp_new_i64(); - TCGv_i64 tcg_wideres =3D tcg_temp_new_i64(); - static NeonGenNarrowFn * const narrowfns[3][2] =3D { - { gen_helper_neon_narrow_high_u8, - gen_helper_neon_narrow_round_high_u8 }, - { gen_helper_neon_narrow_high_u16, - gen_helper_neon_narrow_round_high_u16 }, - { tcg_gen_extrh_i64_i32, do_narrow_round_high_u32 }, - }; - NeonGenNarrowFn *gennarrow =3D narrowfns[size][is_u]; - - read_vec_element(s, tcg_op1, rn, pass, MO_64); - read_vec_element(s, tcg_op2, rm, pass, MO_64); - - gen_neon_addl(size, (opcode =3D=3D 6), tcg_wideres, tcg_op1, tcg_o= p2); - - tcg_res[pass] =3D tcg_temp_new_i32(); - gennarrow(tcg_res[pass], tcg_wideres); - } - - for (pass =3D 0; pass < 2; pass++) { - write_vec_element_i32(s, tcg_res[pass], rd, pass + part, MO_32); - } - clear_vec_high(s, is_q, rd); -} - /* AdvSIMD three different * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0 * +---+---+---+-----------+------+---+------+--------+-----+------+------+ @@ -10899,18 +10894,6 @@ static void disas_simd_three_reg_diff(DisasContext= *s, uint32_t insn) int rd =3D extract32(insn, 0, 5); =20 switch (opcode) { - case 4: /* ADDHN, ADDHN2, RADDHN, RADDHN2 */ - case 6: /* SUBHN, SUBHN2, RSUBHN, RSUBHN2 */ - /* 128 x 128 -> 64 */ - if (size =3D=3D 3) { - unallocated_encoding(s); - return; - } - if (!fp_access_check(s)) { - return; - } - handle_3rd_narrowing(s, is_q, is_u, size, opcode, rd, rn, rm); - break; case 14: /* PMULL, PMULL2 */ if (is_u) { unallocated_encoding(s); @@ -10949,7 +10932,9 @@ static void disas_simd_three_reg_diff(DisasContext = *s, uint32_t insn) case 1: /* SADDW, SADDW2, UADDW, UADDW2 */ case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */ case 3: /* SSUBW, SSUBW2, USUBW, USUBW2 */ + case 4: /* ADDHN, ADDHN2, RADDHN, RADDHN2 */ case 5: /* SABAL, SABAL2, UABAL, UABAL2 */ + case 6: /* SUBHN, SUBHN2, RSUBHN, RSUBHN2 */ case 7: /* SABDL, SABDL2, UABDL, UABDL2 */ case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */ case 9: /* SQDMLAL, SQDMLAL2 */ --=20 2.34.1