From nobody Sun Nov 24 21:51:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1720704259; cv=none; d=zohomail.com; s=zohoarc; b=n7hvce69LRucwIh1AeFvO22cSbMqnv3mXfwMbjPfx7dTgfUX5Y3AIyB+4JhAN4coFW170VzF/gISgdrC6k7FTJerGaKmubBEdgz5tIGCNJtkVsqQNnqkpd6FFJyoTmOU1tjdHigxaCOq+s912eEm23xxhLqeraxbMF9aAhTQ5mM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1720704259; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=nfyQtkiwwsL75LQyY+1VpdO3jlXGa6ezaQj3z/0lsxc=; b=GSdBfrAa46KoLuVNLgP41lRByeLqDe092lroaIP8UOg88OHPB/JzL/QhO3Cd6RKKmkOkZbAPG6vy14kfHNJQouKRf3BIPaq7t5EGPemyehkfSmB51fN+/uWZhj8OvS/RSmn/aDeQ/hkx5pQNUqlGLKA5mYv7lxWb6szN3DtN2+g= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 172070425934886.18271179941053; Thu, 11 Jul 2024 06:24:19 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sRthc-0003BS-Ad; Thu, 11 Jul 2024 09:19:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sRthH-0001mi-Gq for qemu-devel@nongnu.org; Thu, 11 Jul 2024 09:18:55 -0400 Received: from mail-lf1-x129.google.com ([2a00:1450:4864:20::129]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sRth7-000646-Ag for qemu-devel@nongnu.org; Thu, 11 Jul 2024 09:18:55 -0400 Received: by mail-lf1-x129.google.com with SMTP id 2adb3069b0e04-52e94eaf5efso1208097e87.2 for ; Thu, 11 Jul 2024 06:18:35 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4266f736939sm119412025e9.37.2024.07.11.06.18.33 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Jul 2024 06:18:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1720703913; x=1721308713; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=nfyQtkiwwsL75LQyY+1VpdO3jlXGa6ezaQj3z/0lsxc=; b=I7+rZf5SRGBdjXjs1wM+FwiIM2QC+jJhMsFZcjFjlZN7MHKOd62sTpTVmhZvI1q7z+ Gn0PuncP59XV/GdQsYzyJ0T9vzblXNiEalXSWLDqxiriDkViIfXXBAolzZX+l8u5sCsx +1oJx2vnHtYXjVqh3+DGYtBzIXT/MXb9WCwyO0lg6m31dadsxVF+FCyJpjDHSAopkokB nQjJF2feC5lWzBSqJVsM2BeLy5FsoFtI490bYvfxbFXudJdIXi5TI7Q9Ur3ZzIfO27T0 aPcy9xcCpG2QgC4aDsypMxGHUm4r6+qHKYPxBlAPi6NAQkFsotP6U51o1lhOIMtocqKU rs0A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1720703913; x=1721308713; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=nfyQtkiwwsL75LQyY+1VpdO3jlXGa6ezaQj3z/0lsxc=; b=dbQ5Q5cVnbpMJ3VYdGMdlMZL+9geXjsDDDXh/x6vHrgk2k73YqHUCeG7ivbYRwwNfA TysmJKto5js/3VbFr0uiM5H+dfvAwG+CGmVAWqjX6jc/e3s3QtyUG+vmDo5pUGIDJrUE 3HBMY3qZWChZ10nNUH9cAjZtuES8r1Fu1O1OJOk39COO4qnPSUOLbqZl66ye4bOIkQ0J h4/84+wqWMsbiig+WFdNLyxU3PEQIT3Z4ZGM9lxuGtolMrDOeMPREjat/woYdumZj9e5 0yUV1npPociYEGY3asAScbuuydvEekrZV2rHpX2mIzdwwalBb3YGreBVChiDJhWOTjNl poYg== X-Gm-Message-State: AOJu0Yyf9phxeed0KQNbIpVUxtHARa6WkL+JOqHOl8ZkCsOcrPlSkBgH 9O6dPg41XdSAaFQJe+79JtpsYo9gsMkx81oZV7xorMiWlNIVHv9KU1uee7oweB4O1YmWPDMlquD tS6Q= X-Google-Smtp-Source: AGHT+IHewWYSazXg+D/SDJuOFMvaPjGQZTsJOCcLEWkYPc6x73SglLgLRBF1zb90PAKhyajJUbnfTw== X-Received: by 2002:ac2:5f56:0:b0:52b:bf8e:ffea with SMTP id 2adb3069b0e04-52eb99a31f1mr4717141e87.40.1720703913461; Thu, 11 Jul 2024 06:18:33 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 18/24] hw/arm: In STM32L4x5 SOC, connect USART devices to EXTI Date: Thu, 11 Jul 2024 14:18:16 +0100 Message-Id: <20240711131822.3909903-19-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240711131822.3909903-1-peter.maydell@linaro.org> References: <20240711131822.3909903-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::129; envelope-from=peter.maydell@linaro.org; helo=mail-lf1-x129.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1720704260495116600 From: In=C3=A8s Varhol The USART devices were previously connecting their outbound IRQs directly to the CPU because the EXTI wasn't handling direct lines interrupts. Now the USART connects to the EXTI inbound GPIOs, and the EXTI connects its IRQs to the CPU. The existing QTest for the USART (tests/qtest/stm32l4x5_usart-test.c) checks that USART1_IRQ in the CPU is pending when expected so it confirms that the connection through the EXTI still works. Signed-off-by: In=C3=A8s Varhol Reviewed-by: Peter Maydell Message-id: 20240707085927.122867-4-ines.varhol@telecom-paris.fr Signed-off-by: Peter Maydell --- hw/arm/stm32l4x5_soc.c | 24 +++++++++++------------- 1 file changed, 11 insertions(+), 13 deletions(-) diff --git a/hw/arm/stm32l4x5_soc.c b/hw/arm/stm32l4x5_soc.c index 38f7a2d5d9f..fac83d349c8 100644 --- a/hw/arm/stm32l4x5_soc.c +++ b/hw/arm/stm32l4x5_soc.c @@ -81,6 +81,10 @@ static const int exti_irq[NUM_EXTI_IRQ] =3D { #define RCC_BASE_ADDRESS 0x40021000 #define RCC_IRQ 5 =20 +#define EXTI_USART1_IRQ 26 +#define EXTI_UART4_IRQ 29 +#define EXTI_LPUART1_IRQ 31 + static const int exti_or_gates_out[NUM_EXTI_OR_GATES] =3D { 23, 40, 63, 1, }; @@ -129,10 +133,6 @@ static const hwaddr uart_addr[] =3D { =20 #define LPUART_BASE_ADDRESS 0x40008000 =20 -static const int usart_irq[] =3D { 37, 38, 39 }; -static const int uart_irq[] =3D { 52, 53 }; -#define LPUART_IRQ 70 - static void stm32l4x5_soc_initfn(Object *obj) { Stm32l4x5SocState *s =3D STM32L4X5_SOC(obj); @@ -297,6 +297,7 @@ static void stm32l4x5_soc_realize(DeviceState *dev_soc,= Error **errp) } } =20 + /* Connect SYSCFG to EXTI */ for (unsigned i =3D 0; i < GPIO_NUM_PINS; i++) { qdev_connect_gpio_out(DEVICE(&s->syscfg), i, qdev_get_gpio_in(DEVICE(&s->exti), i)); @@ -322,15 +323,10 @@ static void stm32l4x5_soc_realize(DeviceState *dev_so= c, Error **errp) return; } sysbus_mmio_map(busdev, 0, usart_addr[i]); - sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, usart_irq[i= ])); + sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(DEVICE(&s->exti), + EXTI_USART1_IRQ + i= )); } =20 - /* - * TODO: Connect the USARTs, UARTs and LPUART to the EXTI once the EXTI - * can handle other gpio-in than the gpios. (e.g. Direct Lines for the - * usarts) - */ - /* UART devices */ for (int i =3D 0; i < STM_NUM_UARTS; i++) { g_autofree char *name =3D g_strdup_printf("uart%d-out", STM_NUM_US= ARTS + i + 1); @@ -343,7 +339,8 @@ static void stm32l4x5_soc_realize(DeviceState *dev_soc,= Error **errp) return; } sysbus_mmio_map(busdev, 0, uart_addr[i]); - sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, uart_irq[i]= )); + sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(DEVICE(&s->exti), + EXTI_UART4_IRQ + i)= ); } =20 /* LPUART device*/ @@ -356,7 +353,8 @@ static void stm32l4x5_soc_realize(DeviceState *dev_soc,= Error **errp) return; } sysbus_mmio_map(busdev, 0, LPUART_BASE_ADDRESS); - sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, LPUART_IRQ)); + sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(DEVICE(&s->exti), + EXTI_LPUART1_IRQ)); =20 /* APB1 BUS */ create_unimplemented_device("TIM2", 0x40000000, 0x400); --=20 2.34.1