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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4266f736939sm119412025e9.37.2024.07.11.06.18.32 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Jul 2024 06:18:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1720703913; x=1721308713; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=QR2NXELLGLvw8JsL5lqZLeeutghLd/fRnYWQHU0+2J4=; b=Z7PjmKNGkm427d83zFkxUnWOp02sJRTfdsRY8Q8RbkgkyVbPPCw6zS/iFZZAz5vgxh jKh6LRgRzudbA3z8JYCArbszXM979p7wIFaG6vEsYtORk2t37qgxFA6LLFTYRo9vcqXf b9JMTMibbOFdwG5vLjGNZZLBu9C6ymuZ2UhjIxoLo32KzwFDxX1qhGwava5rTihRzCWQ 6oqQeB7hnsQwrbOCXUbOeuUszhk9ft1QgSPhD+9b6MQgwK6jaQNZUrgKPxjGat8Zbl1z sXLcR/1Y12JRzWIRqK13dgZ8pzqquwS6BMCiNCzMrKXD2yPBJmylzAejtI/lgRSIndbC 8BNg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1720703913; x=1721308713; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QR2NXELLGLvw8JsL5lqZLeeutghLd/fRnYWQHU0+2J4=; b=H0Pio1d/xKKEjHAStvY5BKU9gazYdhEkQ7aFZ9a/VFVJMJiL5TqJtwo3bQrc8KhClC z01Kz6+YSWkMkHltKpYWxcBluQMFFdF8YXPWxTQaaYobU4cywTm+/i3QGKasTn+UrQKk bIv9ptZ88E8ptVCz5SsS4g9mG2Lb3U+3Tp6nlT2bvbyJcRzNthPp/7r7tyYGn8yiXa2i spXTq125Lw1ps7lIX9onb5kxhakpUT2VZCbWwVUSm12UCyXneY0BKJo1vkTUBiRmUOpb h1794Z3RCrI2OASt6UqTjCnpX3AyV0hHqxRK+RhaNAClM556TOeJfe5CnLcVN6dU3cjj +rjw== X-Gm-Message-State: AOJu0YxAAA4X1SUaFeWhUczcCHpBr9KclAOrIQh80Q7U2Yw80GTGmNwo YRKS9wGtho8IM5bEDZr8/Kf4kZKf7KYtTEM6ve8HQ9uLX0stWz1XDmjJjZms59bGzh3MwacTJKD 9kMs= X-Google-Smtp-Source: AGHT+IGdaIIvkGyrIbpDccFeeWR0e+pKOZHY2qeh+IFQy7WabksA8OKWVNsG7wvdxCi9/VWFyKX9ig== X-Received: by 2002:a05:600c:1d24:b0:426:698b:791f with SMTP id 5b1f17b1804b1-427981b2287mr23138165e9.3.1720703913021; Thu, 11 Jul 2024 06:18:33 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 17/24] hw/misc: In STM32L4x5 EXTI, handle direct interrupts Date: Thu, 11 Jul 2024 14:18:15 +0100 Message-Id: <20240711131822.3909903-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240711131822.3909903-1-peter.maydell@linaro.org> References: <20240711131822.3909903-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1720704144043116600 From: In=C3=A8s Varhol The previous implementation for EXTI interrupts only handled "configurable" interrupts, like those originating from STM32L4x5 SYSCFG (the only device currently connected to the EXTI up until now). In order to connect STM32L4x5 USART to the EXTI, this commit adds handling for direct interrupts (interrupts without configurable edge). Signed-off-by: In=C3=A8s Varhol Message-id: 20240707085927.122867-3-ines.varhol@telecom-paris.fr Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/misc/stm32l4x5_exti.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/hw/misc/stm32l4x5_exti.c b/hw/misc/stm32l4x5_exti.c index b9a69a69f60..e281841dcf4 100644 --- a/hw/misc/stm32l4x5_exti.c +++ b/hw/misc/stm32l4x5_exti.c @@ -113,6 +113,13 @@ static void stm32l4x5_exti_set_irq(void *opaque, int i= rq, int level) return; } =20 + /* In case of a direct line interrupt */ + if (extract32(exti_romask[bank], irq, 1)) { + qemu_set_irq(s->irq[oirq], level); + return; + } + + /* In case of a configurable interrupt */ if ((level && extract32(s->rtsr[bank], irq, 1)) || (!level && extract32(s->ftsr[bank], irq, 1))) { =20 --=20 2.34.1