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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4266f736939sm119412025e9.37.2024.07.11.06.18.31 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Jul 2024 06:18:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1720703912; x=1721308712; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=vyZll+1B9ZVexjTDYnpEmOSbqEikHHbpXaR8VQUCSuc=; b=Axun5N3lsVTSBvNjJdw4ZscloJod/qmZj8XSd4Hnoz4jsCOfMOotZhvylSPjqnhhaL NEf2fBQj37LgSyn8SoEcWlrW4XZlg02BLNGrtU3r2A8Da6hEQeA4Le9XK8Fwt0ncZOQP 6s2ctIaVstZjdfN7uJH1DQr6syO0DFGw+j3LZmodbMwT675cOPaQQ+7WBORh1EgvsGym LQ6Bk4G6Zb7hoOtIAQtCdXiO9psmUY/HfWWGSGhOKIrIvGOUebzUsBm+31txIXIAtzts 2Dm+3kX42jDiruhAqJGw082Jd838ZSxaNbg6oAaRmjQkHAnODOHP7VRtaTyA705zb76n DSHA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1720703912; x=1721308712; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=vyZll+1B9ZVexjTDYnpEmOSbqEikHHbpXaR8VQUCSuc=; b=RC+KpzY9SvbWL0kzsmWMpaCzSjLl8D7r/ARJLT1cetB2HneNtaLebZ87KO+cQPxXxC USdInO6prD/mnKhPrAY7EI3jq7UBdEZ/ZSMLQvf488y/UXd3n1b7l2Zn5B/rfVkqQMcv 3pMRtxFBUI2oy+5UgNgbxEHB31tCVoOSlR2HRcLzHo36X9Vktlyi0xdbEg8EgzdSFGBT Bm+nsKTki70ubMR3e5Qgqc8a7pTOk2gxaBx4kMuHIVmPiRBq3xM64a9RzQTGb8VVoCiY hLWBWjSraRvOa+lr+wrskjQ6RleXhM9Og2Cj2Cwf01Xl2YfA6fY5skAC+GCfJUBUkIDA 5Gnw== X-Gm-Message-State: AOJu0YxRWlpKM8uq2NYgtNABWYAzA8ms9PCSyR8r8iYoa5j/KFHE9ysq b/1tfvYhynCCyTGDv0VB/FlAf1TW8hkL+PFzBBb687GbpqLpA6dzD+HJSVP+1CQjuGQTImPSr2O B81I= X-Google-Smtp-Source: AGHT+IH4EX55+tBx04YC1QOZ1hPRouUg8cPAGiH9UPisC2mIV0qCJ7qsBVEFc/mt+If7F7fmyt2PQA== X-Received: by 2002:a05:600c:5345:b0:426:602d:a243 with SMTP id 5b1f17b1804b1-426707d8a90mr60422765e9.16.1720703912231; Thu, 11 Jul 2024 06:18:32 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 15/24] accel/tcg: Make TCGCPUOps::cpu_exec_halt mandatory Date: Thu, 11 Jul 2024 14:18:13 +0100 Message-Id: <20240711131822.3909903-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240711131822.3909903-1-peter.maydell@linaro.org> References: <20240711131822.3909903-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1720704085872116600 Now that all targets set TCGCPUOps::cpu_exec_halt, we can make it mandatory and remove the fallback handling that calls cpu_has_work. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/core/tcg-cpu-ops.h | 9 ++++++--- accel/tcg/cpu-exec.c | 11 +++++------ 2 files changed, 11 insertions(+), 9 deletions(-) diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h index 099de3375e3..34318cf0e60 100644 --- a/include/hw/core/tcg-cpu-ops.h +++ b/include/hw/core/tcg-cpu-ops.h @@ -122,10 +122,13 @@ struct TCGCPUOps { * to do when the CPU is in the halted state. * * Return true to indicate that the CPU should now leave halt, false - * if it should remain in the halted state. + * if it should remain in the halted state. (This should generally + * be the same value that cpu_has_work() would return.) * - * If this method is not provided, the default is to do nothing, and - * to leave halt if cpu_has_work() returns true. + * This method must be provided. If the target does not need to + * do anything special for halt, the same function used for its + * CPUClass::has_work method can be used here, as they have the + * same function signature. */ bool (*cpu_exec_halt)(CPUState *cpu); /** diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 6711b58e0b2..245fd6327da 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -682,13 +682,8 @@ static inline bool cpu_handle_halt(CPUState *cpu) #ifndef CONFIG_USER_ONLY if (cpu->halted) { const TCGCPUOps *tcg_ops =3D cpu->cc->tcg_ops; - bool leave_halt; + bool leave_halt =3D tcg_ops->cpu_exec_halt(cpu); =20 - if (tcg_ops->cpu_exec_halt) { - leave_halt =3D tcg_ops->cpu_exec_halt(cpu); - } else { - leave_halt =3D cpu_has_work(cpu); - } if (!leave_halt) { return true; } @@ -1082,6 +1077,10 @@ bool tcg_exec_realizefn(CPUState *cpu, Error **errp) static bool tcg_target_initialized; =20 if (!tcg_target_initialized) { + /* Check mandatory TCGCPUOps handlers */ +#ifndef CONFIG_USER_ONLY + assert(cpu->cc->tcg_ops->cpu_exec_halt); +#endif /* !CONFIG_USER_ONLY */ cpu->cc->tcg_ops->initialize(); tcg_target_initialized =3D true; } --=20 2.34.1