From nobody Sun Nov 24 21:26:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1720704282; cv=none; d=zohomail.com; s=zohoarc; b=NwUAJ3TFz63q+9E1fJ6m2++Y7B8v5au+XxcSJxu+xJLeM/glNP1iWoqfFLlX94dOop5N0C8F+dq+zmhzPrLOnNFmW7tVyq/6VRh5+f0mx6dqYCOmYo/H4/+K+qdKkGmD5su2UyfFOe/SZR8QZ013Qo26UULtHUjbagwP4Kcqv9o= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1720704282; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=nFYyrjsNrLUd84ygFglfo4UEH7zDocaQimrRcj1rdrk=; b=ehHU6bQDSZqsItStN8EOE78+Ylm2T0ZK6LGH6LQ0rz5eSrhopoxO9PX2QKUCYsTwrFaVyxSPiNBwmOGcVhO9d9/elhfo3AIpKWCSVMA8ZQdZZnB6xhyABaDCU0lilVz9IBaViOYXQK2wzwGCC5VGEfbC73rvlqzHSYe+40U55Nk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1720704282698256.82285406810126; Thu, 11 Jul 2024 06:24:42 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sRthO-0002Bn-JR; Thu, 11 Jul 2024 09:19:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sRthD-0001WI-93 for qemu-devel@nongnu.org; Thu, 11 Jul 2024 09:18:51 -0400 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sRth7-00063Q-B3 for qemu-devel@nongnu.org; Thu, 11 Jul 2024 09:18:50 -0400 Received: by mail-wm1-x32b.google.com with SMTP id 5b1f17b1804b1-4266182a9d7so5441345e9.0 for ; Thu, 11 Jul 2024 06:18:30 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4266f736939sm119412025e9.37.2024.07.11.06.18.28 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Jul 2024 06:18:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1720703909; x=1721308709; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=nFYyrjsNrLUd84ygFglfo4UEH7zDocaQimrRcj1rdrk=; b=j9BzpUSA38kTZVnZ30oIa01V10Zvxk1NLMBqQZLgjevKYcGCaKw/nXIcrXHcVUbly+ BETVa9PPdQL/wskZERc5o2I147PyF8PUCGrTkbgtorDyMA1M8cHjHzZ0pMlCHfLw6HMz Vy575bPYiMvyHBzh0hVpIeWvD/7NDPr1M3EjitVBXpmx4Qg+Om5IyLxgYVa6fVjIUAFR SccwFqifvsoBVeTtMtCV+lFCy6hHhR1DPAEMZuXr1N0suSVTnINX1fdxgEgod9hVrZfc x7HLys9zIv5SP5X3Nm2/I1cQNfJhV6pEuR3FuREuYmJXNlnZf3W8jyDh3DKNJhjFBBf/ iOVA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1720703909; x=1721308709; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=nFYyrjsNrLUd84ygFglfo4UEH7zDocaQimrRcj1rdrk=; b=W+iFFfDpoWIiPMt2fP4omOD5qdS5usr1hTzP1wV/akvHYoT4AtaTyiCHIjxIc+lu3Z G81+9aHlIBufHPxc9sAmnQIymxhHGUI4GNcXig2RPN7h0Ooi5kPMBfLEDH6FLVk9EfOR 4i5j80olquejg38cqu3hfDHKxf3gFFYQaVxs/3rJbBqpJAUXMHQdy0/viYGcvAATqzs+ +50izIGx9aHj3YOAVqecglNMPeS1xQs6yIzAlik36XQczTUKmPhr3OB86tXc9HRYZP3p VxiYMm0Ydt12EXu0wf4rK11iTZqbT6VmEiKL8mK90B4b+5MGXb2U8LOzY8J1QpIHcDRE gdvQ== X-Gm-Message-State: AOJu0YzPfX/MDNnmU/qXpdqGldL5N3k0dSgEBeCHoL2un5oWc2k7yXLx lR2qEczufxJk0bS6rbbWVhWIOAkygHNNYtMiYZLX+CyuTLMG5WhGsr6fkoRh9fEQfCwUEJQsBWE mG1k= X-Google-Smtp-Source: AGHT+IFDt5fPKTsd7j/Jd0ZGDHV2qARJrV8KuvqPDIaItvgJZrgvI2p7FXYDZcckLhnnnNddHvJYVA== X-Received: by 2002:a05:600c:4a98:b0:426:6ea0:d5b8 with SMTP id 5b1f17b1804b1-426708f2012mr55968125e9.29.1720703909314; Thu, 11 Jul 2024 06:18:29 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 09/24] target/arm: Allow FPCR bits that aren't in FPSCR Date: Thu, 11 Jul 2024 14:18:07 +0100 Message-Id: <20240711131822.3909903-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240711131822.3909903-1-peter.maydell@linaro.org> References: <20240711131822.3909903-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1720704284901116600 Content-Type: text/plain; charset="utf-8" In order to allow FPCR bits that aren't in the FPSCR (like the new bits that are defined for FEAT_AFP), we need to make sure that writes to the FPSCR only write to the bits of FPCR that are architecturally mapped, and not the others. Implement this with a new function vfp_set_fpcr_masked() which takes a mask of which bits to update. (We could do the same for FPSR, but we leave that until we actually are likely to need it.) Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20240628142347.1283015-10-peter.maydell@linaro.org --- target/arm/vfp_helper.c | 54 ++++++++++++++++++++++++++--------------- 1 file changed, 34 insertions(+), 20 deletions(-) diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c index cbe69ae3fe3..b3698da8ca7 100644 --- a/target/arm/vfp_helper.c +++ b/target/arm/vfp_helper.c @@ -113,11 +113,12 @@ static void vfp_set_fpsr_to_host(CPUARMState *env, ui= nt32_t val) set_float_exception_flags(0, &env->vfp.standard_fp_status_f16); } =20 -static void vfp_set_fpcr_to_host(CPUARMState *env, uint32_t val) +static void vfp_set_fpcr_to_host(CPUARMState *env, uint32_t val, uint32_t = mask) { uint64_t changed =3D env->vfp.fpcr; =20 changed ^=3D val; + changed &=3D mask; if (changed & (3 << 22)) { int i =3D (val >> 22) & 3; switch (i) { @@ -167,7 +168,7 @@ static void vfp_set_fpsr_to_host(CPUARMState *env, uint= 32_t val) { } =20 -static void vfp_set_fpcr_to_host(CPUARMState *env, uint32_t val) +static void vfp_set_fpcr_to_host(CPUARMState *env, uint32_t val, uint32_t = mask) { } =20 @@ -239,8 +240,13 @@ void vfp_set_fpsr(CPUARMState *env, uint32_t val) env->vfp.fpsr =3D val; } =20 -void vfp_set_fpcr(CPUARMState *env, uint32_t val) +static void vfp_set_fpcr_masked(CPUARMState *env, uint32_t val, uint32_t m= ask) { + /* + * We only set FPCR bits defined by mask, and leave the others alone. + * We assume the mask is sensible (e.g. doesn't try to set only + * part of a field) + */ ARMCPU *cpu =3D env_archcpu(env); =20 /* When ARMv8.2-FP16 is not supported, FZ16 is RES0. */ @@ -248,22 +254,24 @@ void vfp_set_fpcr(CPUARMState *env, uint32_t val) val &=3D ~FPCR_FZ16; } =20 - vfp_set_fpcr_to_host(env, val); + vfp_set_fpcr_to_host(env, val, mask); =20 - if (!arm_feature(env, ARM_FEATURE_M)) { - /* - * Short-vector length and stride; on M-profile these bits - * are used for different purposes. - * We can't make this conditional be "if MVFR0.FPShVec !=3D 0", - * because in v7A no-short-vector-support cores still had to - * allow Stride/Len to be written with the only effect that - * some insns are required to UNDEF if the guest sets them. - */ - env->vfp.vec_len =3D extract32(val, 16, 3); - env->vfp.vec_stride =3D extract32(val, 20, 2); - } else if (cpu_isar_feature(aa32_mve, cpu)) { - env->v7m.ltpsize =3D extract32(val, FPCR_LTPSIZE_SHIFT, - FPCR_LTPSIZE_LENGTH); + if (mask & (FPCR_LEN_MASK | FPCR_STRIDE_MASK)) { + if (!arm_feature(env, ARM_FEATURE_M)) { + /* + * Short-vector length and stride; on M-profile these bits + * are used for different purposes. + * We can't make this conditional be "if MVFR0.FPShVec !=3D 0", + * because in v7A no-short-vector-support cores still had to + * allow Stride/Len to be written with the only effect that + * some insns are required to UNDEF if the guest sets them. + */ + env->vfp.vec_len =3D extract32(val, 16, 3); + env->vfp.vec_stride =3D extract32(val, 20, 2); + } else if (cpu_isar_feature(aa32_mve, cpu)) { + env->v7m.ltpsize =3D extract32(val, FPCR_LTPSIZE_SHIFT, + FPCR_LTPSIZE_LENGTH); + } } =20 /* @@ -276,12 +284,18 @@ void vfp_set_fpcr(CPUARMState *env, uint32_t val) * bits. */ val &=3D FPCR_AHP | FPCR_DN | FPCR_FZ | FPCR_RMODE_MASK | FPCR_FZ16; - env->vfp.fpcr =3D val; + env->vfp.fpcr &=3D ~mask; + env->vfp.fpcr |=3D val; +} + +void vfp_set_fpcr(CPUARMState *env, uint32_t val) +{ + vfp_set_fpcr_masked(env, val, MAKE_64BIT_MASK(0, 32)); } =20 void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val) { - vfp_set_fpcr(env, val & FPSCR_FPCR_MASK); + vfp_set_fpcr_masked(env, val, FPSCR_FPCR_MASK); vfp_set_fpsr(env, val & FPSCR_FPSR_MASK); } =20 --=20 2.34.1