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Thu, 11 Jul 2024 15:31:40 -0700 (PDT) From: Atish Patra Date: Thu, 11 Jul 2024 15:31:10 -0700 Subject: [PATCH v8 07/13] target/riscv: Implement privilege mode filtering for cycle/instret MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240711-smcntrpmf_v7-v8-7-b7c38ae7b263@rivosinc.com> References: <20240711-smcntrpmf_v7-v8-0-b7c38ae7b263@rivosinc.com> In-Reply-To: <20240711-smcntrpmf_v7-v8-0-b7c38ae7b263@rivosinc.com> To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: palmer@dabbelt.com, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, bin.meng@windriver.com, dbarboza@ventanamicro.com, alistair.francis@wdc.com X-Mailer: b4 0.15-dev-13183 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=atishp@rivosinc.com; helo=mail-pl1-x62e.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @rivosinc-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1720737272716116600 Privilege mode filtering can also be emulated for cycle/instret by tracking host_ticks/icount during each privilege mode switch. This patch implements that for both cycle/instret and mhpmcounters. The first one requires Smcntrpmf while the other one requires Sscofpmf to be enabled. The cycle/instret are still computed using host ticks when icount is not enabled. Otherwise, they are computed using raw icount which is more accurate in icount mode. Co-Developed-by: Rajnesh Kanwal Signed-off-by: Rajnesh Kanwal Reviewed-by: Daniel Henrique Barboza Acked-by: Alistair Francis Signed-off-by: Atish Patra --- target/riscv/cpu.h | 11 +++++ target/riscv/cpu_helper.c | 9 +++- target/riscv/csr.c | 117 ++++++++++++++++++++++++++++++++----------= ---- target/riscv/pmu.c | 92 ++++++++++++++++++++++++++++++++++++ target/riscv/pmu.h | 2 + 5 files changed, 194 insertions(+), 37 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index c5d289e5f4b9..d56d640b06be 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -158,6 +158,15 @@ typedef struct PMUCTRState { target_ulong irq_overflow_left; } PMUCTRState; =20 +typedef struct PMUFixedCtrState { + /* Track cycle and icount for each privilege mode */ + uint64_t counter[4]; + uint64_t counter_prev[4]; + /* Track cycle and icount for each privilege mode when V =3D 1*/ + uint64_t counter_virt[2]; + uint64_t counter_virt_prev[2]; +} PMUFixedCtrState; + struct CPUArchState { target_ulong gpr[32]; target_ulong gprh[32]; /* 64 top bits of the 128-bit registers */ @@ -354,6 +363,8 @@ struct CPUArchState { /* PMU event selector configured values for RV32 */ target_ulong mhpmeventh_val[RV_MAX_MHPMEVENTS]; =20 + PMUFixedCtrState pmu_fixed_ctrs[2]; + target_ulong sscratch; target_ulong mscratch; =20 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 10d3fdaed376..395a1d914061 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -695,9 +695,14 @@ void riscv_cpu_set_mode(CPURISCVState *env, target_ulo= ng newpriv, bool virt_en) { g_assert(newpriv <=3D PRV_M && newpriv !=3D PRV_RESERVED); =20 - if (icount_enabled() && newpriv !=3D env->priv) { - riscv_itrigger_update_priv(env); + if (newpriv !=3D env->priv || env->virt_enabled !=3D virt_en) { + if (icount_enabled()) { + riscv_itrigger_update_priv(env); + } + + riscv_pmu_update_fixed_ctrs(env, newpriv, virt_en); } + /* tlb_flush is unnecessary as mode is contained in mmu_idx */ env->priv =3D newpriv; env->xl =3D cpu_recompute_xl(env); diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 121996edab4b..53f1a7ff00db 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -787,36 +787,16 @@ static RISCVException write_vcsr(CPURISCVState *env, = int csrno, return RISCV_EXCP_NONE; } =20 +#if defined(CONFIG_USER_ONLY) /* User Timers and Counters */ -static target_ulong get_ticks(bool shift, bool instructions) +static target_ulong get_ticks(bool shift) { - int64_t val; - target_ulong result; - -#if !defined(CONFIG_USER_ONLY) - if (icount_enabled()) { - if (instructions) { - val =3D icount_get_raw(); - } else { - val =3D icount_get(); - } - } else { - val =3D cpu_get_host_ticks(); - } -#else - val =3D cpu_get_host_ticks(); -#endif - - if (shift) { - result =3D val >> 32; - } else { - result =3D val; - } + int64_t val =3D cpu_get_host_ticks(); + target_ulong result =3D shift ? val >> 32 : val; =20 return result; } =20 -#if defined(CONFIG_USER_ONLY) static RISCVException read_time(CPURISCVState *env, int csrno, target_ulong *val) { @@ -834,14 +814,14 @@ static RISCVException read_timeh(CPURISCVState *env, = int csrno, static RISCVException read_hpmcounter(CPURISCVState *env, int csrno, target_ulong *val) { - *val =3D get_ticks(false, (csrno =3D=3D CSR_INSTRET)); + *val =3D get_ticks(false); return RISCV_EXCP_NONE; } =20 static RISCVException read_hpmcounterh(CPURISCVState *env, int csrno, target_ulong *val) { - *val =3D get_ticks(true, (csrno =3D=3D CSR_INSTRETH)); + *val =3D get_ticks(true); return RISCV_EXCP_NONE; } =20 @@ -1025,17 +1005,82 @@ static RISCVException write_mhpmeventh(CPURISCVStat= e *env, int csrno, return RISCV_EXCP_NONE; } =20 +static target_ulong riscv_pmu_ctr_get_fixed_counters_val(CPURISCVState *en= v, + int counter_idx, + bool upper_half) +{ + int inst =3D riscv_pmu_ctr_monitor_instructions(env, counter_idx); + uint64_t *counter_arr_virt =3D env->pmu_fixed_ctrs[inst].counter_virt; + uint64_t *counter_arr =3D env->pmu_fixed_ctrs[inst].counter; + target_ulong result =3D 0; + uint64_t curr_val =3D 0; + uint64_t cfg_val =3D 0; + + if (counter_idx =3D=3D 0) { + cfg_val =3D upper_half ? ((uint64_t)env->mcyclecfgh << 32) : + env->mcyclecfg; + } else if (counter_idx =3D=3D 2) { + cfg_val =3D upper_half ? ((uint64_t)env->minstretcfgh << 32) : + env->minstretcfg; + } else { + cfg_val =3D upper_half ? + ((uint64_t)env->mhpmeventh_val[counter_idx] << 32) : + env->mhpmevent_val[counter_idx]; + cfg_val &=3D MHPMEVENT_FILTER_MASK; + } + + if (!cfg_val) { + if (icount_enabled()) { + curr_val =3D inst ? icount_get_raw() : icount_get(); + } else { + curr_val =3D cpu_get_host_ticks(); + } + + goto done; + } + + if (!(cfg_val & MCYCLECFG_BIT_MINH)) { + curr_val +=3D counter_arr[PRV_M]; + } + + if (!(cfg_val & MCYCLECFG_BIT_SINH)) { + curr_val +=3D counter_arr[PRV_S]; + } + + if (!(cfg_val & MCYCLECFG_BIT_UINH)) { + curr_val +=3D counter_arr[PRV_U]; + } + + if (!(cfg_val & MCYCLECFG_BIT_VSINH)) { + curr_val +=3D counter_arr_virt[PRV_S]; + } + + if (!(cfg_val & MCYCLECFG_BIT_VUINH)) { + curr_val +=3D counter_arr_virt[PRV_U]; + } + +done: + if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { + result =3D upper_half ? curr_val >> 32 : curr_val; + } else { + result =3D curr_val; + } + + return result; +} + static RISCVException write_mhpmcounter(CPURISCVState *env, int csrno, target_ulong val) { int ctr_idx =3D csrno - CSR_MCYCLE; PMUCTRState *counter =3D &env->pmu_ctrs[ctr_idx]; uint64_t mhpmctr_val =3D val; - bool instr =3D riscv_pmu_ctr_monitor_instructions(env, ctr_idx); =20 counter->mhpmcounter_val =3D val; - if (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) || instr) { - counter->mhpmcounter_prev =3D get_ticks(false, instr); + if (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) || + riscv_pmu_ctr_monitor_instructions(env, ctr_idx)) { + counter->mhpmcounter_prev =3D riscv_pmu_ctr_get_fixed_counters_val= (env, + ctr_idx, f= alse); if (ctr_idx > 2) { if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { mhpmctr_val =3D mhpmctr_val | @@ -1058,12 +1103,13 @@ static RISCVException write_mhpmcounterh(CPURISCVSt= ate *env, int csrno, PMUCTRState *counter =3D &env->pmu_ctrs[ctr_idx]; uint64_t mhpmctr_val =3D counter->mhpmcounter_val; uint64_t mhpmctrh_val =3D val; - bool instr =3D riscv_pmu_ctr_monitor_instructions(env, ctr_idx); =20 counter->mhpmcounterh_val =3D val; mhpmctr_val =3D mhpmctr_val | (mhpmctrh_val << 32); - if (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) || instr) { - counter->mhpmcounterh_prev =3D get_ticks(true, instr); + if (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) || + riscv_pmu_ctr_monitor_instructions(env, ctr_idx)) { + counter->mhpmcounterh_prev =3D riscv_pmu_ctr_get_fixed_counters_va= l(env, + ctr_idx, = true); if (ctr_idx > 2) { riscv_pmu_setup_timer(env, mhpmctr_val, ctr_idx); } @@ -1082,7 +1128,6 @@ static RISCVException riscv_pmu_read_ctr(CPURISCVStat= e *env, target_ulong *val, counter->mhpmcounter_prev; target_ulong ctr_val =3D upper_half ? counter->mhpmcounterh_val : counter->mhpmcounter_val; - bool instr =3D riscv_pmu_ctr_monitor_instructions(env, ctr_idx); =20 if (get_field(env->mcountinhibit, BIT(ctr_idx))) { /* @@ -1103,8 +1148,10 @@ static RISCVException riscv_pmu_read_ctr(CPURISCVSta= te *env, target_ulong *val, * The kernel computes the perf delta by subtracting the current value= from * the value it initialized previously (ctr_val). */ - if (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) || instr) { - *val =3D get_ticks(upper_half, instr) - ctr_prev + ctr_val; + if (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) || + riscv_pmu_ctr_monitor_instructions(env, ctr_idx)) { + *val =3D riscv_pmu_ctr_get_fixed_counters_val(env, ctr_idx, upper_= half) - + ctr_prev + ctr_val; } else { *val =3D ctr_val; } diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c index 0e7d58b8a5c2..ac648cff8d7c 100644 --- a/target/riscv/pmu.c +++ b/target/riscv/pmu.c @@ -19,6 +19,7 @@ #include "qemu/osdep.h" #include "qemu/log.h" #include "qemu/error-report.h" +#include "qemu/timer.h" #include "cpu.h" #include "pmu.h" #include "sysemu/cpu-timers.h" @@ -176,6 +177,97 @@ static int riscv_pmu_incr_ctr_rv64(RISCVCPU *cpu, uint= 32_t ctr_idx) return 0; } =20 +/* + * Information needed to update counters: + * new_priv, new_virt: To correctly save starting snapshot for the newly + * started mode. Look at array being indexed with new= prv. + * old_priv, old_virt: To correctly select previous snapshot for old priv + * and compute delta. Also to select correct counter + * to inc. Look at arrays being indexed with env->pri= v. + * + * To avoid the complexity of calling this function, we assume that + * env->priv and env->virt_enabled contain old priv and old virt and + * new priv and new virt values are passed in as arguments. + */ +static void riscv_pmu_icount_update_priv(CPURISCVState *env, + target_ulong newpriv, bool new_vi= rt) +{ + uint64_t *snapshot_prev, *snapshot_new; + uint64_t current_icount; + uint64_t *counter_arr; + uint64_t delta; + + if (icount_enabled()) { + current_icount =3D icount_get_raw(); + } else { + current_icount =3D cpu_get_host_ticks(); + } + + if (env->virt_enabled) { + counter_arr =3D env->pmu_fixed_ctrs[1].counter_virt; + snapshot_prev =3D env->pmu_fixed_ctrs[1].counter_virt_prev; + } else { + counter_arr =3D env->pmu_fixed_ctrs[1].counter; + snapshot_prev =3D env->pmu_fixed_ctrs[1].counter_prev; + } + + if (new_virt) { + snapshot_new =3D env->pmu_fixed_ctrs[1].counter_virt_prev; + } else { + snapshot_new =3D env->pmu_fixed_ctrs[1].counter_prev; + } + + /* + * new_priv can be same as env->priv. So we need to calculate + * delta first before updating snapshot_new[new_priv]. + */ + delta =3D current_icount - snapshot_prev[env->priv]; + snapshot_new[newpriv] =3D current_icount; + + counter_arr[env->priv] +=3D delta; +} + +static void riscv_pmu_cycle_update_priv(CPURISCVState *env, + target_ulong newpriv, bool new_vir= t) +{ + uint64_t *snapshot_prev, *snapshot_new; + uint64_t current_ticks; + uint64_t *counter_arr; + uint64_t delta; + + if (icount_enabled()) { + current_ticks =3D icount_get(); + } else { + current_ticks =3D cpu_get_host_ticks(); + } + + if (env->virt_enabled) { + counter_arr =3D env->pmu_fixed_ctrs[0].counter_virt; + snapshot_prev =3D env->pmu_fixed_ctrs[0].counter_virt_prev; + } else { + counter_arr =3D env->pmu_fixed_ctrs[0].counter; + snapshot_prev =3D env->pmu_fixed_ctrs[0].counter_prev; + } + + if (new_virt) { + snapshot_new =3D env->pmu_fixed_ctrs[0].counter_virt_prev; + } else { + snapshot_new =3D env->pmu_fixed_ctrs[0].counter_prev; + } + + delta =3D current_ticks - snapshot_prev[env->priv]; + snapshot_new[newpriv] =3D current_ticks; + + counter_arr[env->priv] +=3D delta; +} + +void riscv_pmu_update_fixed_ctrs(CPURISCVState *env, target_ulong newpriv, + bool new_virt) +{ + riscv_pmu_cycle_update_priv(env, newpriv, new_virt); + riscv_pmu_icount_update_priv(env, newpriv, new_virt); +} + int riscv_pmu_incr_ctr(RISCVCPU *cpu, enum riscv_pmu_event_idx event_idx) { uint32_t ctr_idx; diff --git a/target/riscv/pmu.h b/target/riscv/pmu.h index 7c0ad661e050..ca40cfeed647 100644 --- a/target/riscv/pmu.h +++ b/target/riscv/pmu.h @@ -34,5 +34,7 @@ int riscv_pmu_incr_ctr(RISCVCPU *cpu, enum riscv_pmu_even= t_idx event_idx); void riscv_pmu_generate_fdt_node(void *fdt, uint32_t cmask, char *pmu_name= ); int riscv_pmu_setup_timer(CPURISCVState *env, uint64_t value, uint32_t ctr_idx); +void riscv_pmu_update_fixed_ctrs(CPURISCVState *env, target_ulong newpriv, + bool new_virt); =20 #endif /* RISCV_PMU_H */ --=20 2.34.1