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Thu, 11 Jul 2024 15:31:39 -0700 (PDT) From: Atish Patra Date: Thu, 11 Jul 2024 15:31:09 -0700 Subject: [PATCH v8 06/13] target/riscv: Only set INH fields if priv mode is available MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240711-smcntrpmf_v7-v8-6-b7c38ae7b263@rivosinc.com> References: <20240711-smcntrpmf_v7-v8-0-b7c38ae7b263@rivosinc.com> In-Reply-To: <20240711-smcntrpmf_v7-v8-0-b7c38ae7b263@rivosinc.com> To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: palmer@dabbelt.com, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, bin.meng@windriver.com, dbarboza@ventanamicro.com, alistair.francis@wdc.com X-Mailer: b4 0.15-dev-13183 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=atishp@rivosinc.com; helo=mail-pl1-x634.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @rivosinc-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1720737226321116600 Currently, the INH fields are set in mhpmevent uncoditionally without checking if a particular priv mode is supported or not. Suggested-by: Alistair Francis Signed-off-by: Atish Patra Acked-by: Alistair Francis --- target/riscv/csr.c | 29 +++++++++++++++++++++++++---- 1 file changed, 25 insertions(+), 4 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index b814d176cbb8..121996edab4b 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -967,13 +967,24 @@ static RISCVException write_mhpmevent(CPURISCVState *= env, int csrno, { int evt_index =3D csrno - CSR_MCOUNTINHIBIT; uint64_t mhpmevt_val =3D val; - - env->mhpmevent_val[evt_index] =3D val; + uint64_t inh_avail_mask; =20 if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { + env->mhpmevent_val[evt_index] =3D val; mhpmevt_val =3D mhpmevt_val | ((uint64_t)env->mhpmeventh_val[evt_index] << 32); + } else { + inh_avail_mask =3D ~MHPMEVENT_FILTER_MASK | MHPMEVENT_BIT_MINH; + inh_avail_mask |=3D riscv_has_ext(env, RVU) ? MHPMEVENT_BIT_UINH := 0; + inh_avail_mask |=3D riscv_has_ext(env, RVS) ? MHPMEVENT_BIT_SINH := 0; + inh_avail_mask |=3D (riscv_has_ext(env, RVH) && + riscv_has_ext(env, RVU)) ? MHPMEVENT_BIT_VUINH = : 0; + inh_avail_mask |=3D (riscv_has_ext(env, RVH) && + riscv_has_ext(env, RVS)) ? MHPMEVENT_BIT_VSINH = : 0; + mhpmevt_val =3D val & inh_avail_mask; + env->mhpmevent_val[evt_index] =3D mhpmevt_val; } + riscv_pmu_update_event_map(env, mhpmevt_val, evt_index); =20 return RISCV_EXCP_NONE; @@ -993,11 +1004,21 @@ static RISCVException write_mhpmeventh(CPURISCVState= *env, int csrno, target_ulong val) { int evt_index =3D csrno - CSR_MHPMEVENT3H + 3; - uint64_t mhpmevth_val =3D val; + uint64_t mhpmevth_val; uint64_t mhpmevt_val =3D env->mhpmevent_val[evt_index]; + target_ulong inh_avail_mask =3D (target_ulong)(~MHPMEVENTH_FILTER_MASK= | + MHPMEVENTH_BIT_MINH); + + inh_avail_mask |=3D riscv_has_ext(env, RVU) ? MHPMEVENTH_BIT_UINH : 0; + inh_avail_mask |=3D riscv_has_ext(env, RVS) ? MHPMEVENTH_BIT_SINH : 0; + inh_avail_mask |=3D (riscv_has_ext(env, RVH) && + riscv_has_ext(env, RVU)) ? MHPMEVENTH_BIT_VUINH : 0; + inh_avail_mask |=3D (riscv_has_ext(env, RVH) && + riscv_has_ext(env, RVS)) ? MHPMEVENTH_BIT_VSINH : 0; =20 + mhpmevth_val =3D val & inh_avail_mask; mhpmevt_val =3D mhpmevt_val | (mhpmevth_val << 32); - env->mhpmeventh_val[evt_index] =3D val; + env->mhpmeventh_val[evt_index] =3D mhpmevth_val; =20 riscv_pmu_update_event_map(env, mhpmevt_val, evt_index); =20 --=20 2.34.1