From nobody Sun Nov 24 20:57:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1720737248; cv=none; d=zohomail.com; s=zohoarc; b=E3CHnDEhovZ3BEu0VmKsA+ODLaeMPBYgA+f8bziHxzE8SuqcL7VljR2D5fy21nmlHJHTePFD7xRJHhPIuUw4DjscOCxpSbzMSt8V2+JpA8hP3UZ56x8f/lQqaPJwRzvHgp/3iFze4mpPzqCpuk8a3X+DdjvIc4auHLPT8MVp8HE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1720737248; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=sq6ZPtLM8cZpjKl0EALHfFJyJDausZH14SH/XMvmzaY=; b=RezZnkYJHPtTtxu/I0YJeckFDHy12o6J+Sk8ggexeUyB6gb3+ccHo+Bd4Uq4QWahV0Y3gMfglQhLGjWECQPJSLPERy1HYn302lYjiatCuqed1DmKcmX80gwwh1Mfm1zEj/9RSz2jr76VOWInjJPyiLVA4J+rcPqIlfAisX4zTxk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1720737248835486.42141910794817; Thu, 11 Jul 2024 15:34:08 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sS2KA-00005E-R5; Thu, 11 Jul 2024 18:31:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sS2K8-0008R8-T4 for qemu-devel@nongnu.org; Thu, 11 Jul 2024 18:31:37 -0400 Received: from mail-pl1-x629.google.com ([2607:f8b0:4864:20::629]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sS2K6-0001YB-56 for qemu-devel@nongnu.org; Thu, 11 Jul 2024 18:31:36 -0400 Received: by mail-pl1-x629.google.com with SMTP id d9443c01a7336-1fb70169c23so12917635ad.1 for ; Thu, 11 Jul 2024 15:31:32 -0700 (PDT) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1fbb6b34ca2sm55161565ad.53.2024.07.11.15.31.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Jul 2024 15:31:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1720737091; x=1721341891; darn=nongnu.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=sq6ZPtLM8cZpjKl0EALHfFJyJDausZH14SH/XMvmzaY=; b=i8GhUYZHr9HnomUP8iloRqDQMc/lAqv1RxmTJN3Qu4nNdvsyXzP0sqo5p4YLiqJ34S gZ0n5rhvN2BFR0syGPnkAT0XWJcs57OeT56XLUgGYch+FN0BZEcKmICJnhuec1hY4UzH wcr3Ym1H963JZGRTNmwrT9Zxb4wdg0e+3Uabg4lqFBsIHVlFaPWat/R9yO29k8fcaDOA m9zdIXUeD0437jeBkrQDn40fH8rAl3+wyAXgdrJ++LcOcW0dCbj4s6DXCMLQ2wspPJUH VMgeHD98ijqer0K53RpHwYTPqOafpDLyHs1fiavtd/kNwWdRHo5gFmRxr/W9hFwcatRq gdhA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1720737091; x=1721341891; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=sq6ZPtLM8cZpjKl0EALHfFJyJDausZH14SH/XMvmzaY=; b=m64ikvN/xGwLkVA7U0xaN/SL0JatBTuhLex+wc9uqMFKS38GcJYTxFFz7vE9rcWT1W Yrw9kE97DKbY4G2I/d9xut/9cari2qRYvSjXEwZqaboqEBKb/zNUVkIDIICMzdV/qZWL RT1eSPvEItLM0a7oNidDeqHY6V7h4xDQxyA9QSltriT8oxOIeRUbSf/qRpf4pEj9mD/6 p+6J+MLVzxlNtwn5fQ2Gtj5OxWqW/GQqvUubzg/sQw0nhT1skdvhnuL98LAc6IPL94ZG MGQryrZvlRSMrj50Z88EErfo4n4FjtUMFS/muYZcWUAJHVbdOg5spsOj2PWHf4ln3KC6 4tMw== X-Forwarded-Encrypted: i=1; AJvYcCXpQLA2+B5T/8xVop5Oe7AwAsfTI1GO+dc1UFbTnflL5ZUMKFhxSdYd0uhKYWjBeQKFFMN+fNFlD+dL4CsiMs8LKhwxWJw= X-Gm-Message-State: AOJu0YzYdFc5itE4Jdgp/Cwqc8hRN1frSzTg98o9uYjpNaLYC5wKAcvQ prynvpV9MIhs1WunwjfJXAvSW46lR4XE/gOzswgoCC/Uzksp+FjORtjm3cQMad8= X-Google-Smtp-Source: AGHT+IEtRllJw58z5xoeI0uAXNqfsZR17+zreonrSt2yP+iSgMMPrIVcYAX/uaxpldPIaUa4WHsMdQ== X-Received: by 2002:a17:902:dacb:b0:1fb:284b:b39a with SMTP id d9443c01a7336-1fbb6d044a5mr91533685ad.21.1720737090565; Thu, 11 Jul 2024 15:31:30 -0700 (PDT) From: Atish Patra Date: Thu, 11 Jul 2024 15:31:04 -0700 Subject: [PATCH v8 01/13] target/riscv: Combine set_mode and set_virt functions. MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240711-smcntrpmf_v7-v8-1-b7c38ae7b263@rivosinc.com> References: <20240711-smcntrpmf_v7-v8-0-b7c38ae7b263@rivosinc.com> In-Reply-To: <20240711-smcntrpmf_v7-v8-0-b7c38ae7b263@rivosinc.com> To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: palmer@dabbelt.com, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, bin.meng@windriver.com, dbarboza@ventanamicro.com, alistair.francis@wdc.com X-Mailer: b4 0.15-dev-13183 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=atishp@rivosinc.com; helo=mail-pl1-x629.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @rivosinc-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1720737250453116600 From: Rajnesh Kanwal Combining riscv_cpu_set_virt_enabled() and riscv_cpu_set_mode() functions. This is to make complete mode change information available through a single function. This allows to easily differentiate between HS->VS, VS->HS and VS->VS transitions when executing state update codes. For example: One use-case which inspired this change is to update mode-specific instruction and cycle counters which requires information of both prev mode and current mode. Signed-off-by: Rajnesh Kanwal Reviewed-by: Alistair Francis Reviewed-by: Daniel Henrique Barboza --- target/riscv/cpu.h | 2 +- target/riscv/cpu_helper.c | 57 +++++++++++++++++++++++--------------------= ---- target/riscv/op_helper.c | 17 +++++--------- 3 files changed, 35 insertions(+), 41 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 90b8f1b08f83..46faefd24e09 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -544,7 +544,7 @@ void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, = uint32_t priv, RISCVException smstateen_acc_ok(CPURISCVState *env, int index, uint64_t bi= t); #endif /* !CONFIG_USER_ONLY */ =20 -void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv); +void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv, bool vir= t_en); =20 void riscv_translate_init(void); G_NORETURN void riscv_raise_exception(CPURISCVState *env, diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 6709622dd3ab..10d3fdaed376 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -619,30 +619,6 @@ void riscv_cpu_set_geilen(CPURISCVState *env, target_u= long geilen) env->geilen =3D geilen; } =20 -/* This function can only be called to set virt when RVH is enabled */ -void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable) -{ - /* Flush the TLB on all virt mode changes. */ - if (env->virt_enabled !=3D enable) { - tlb_flush(env_cpu(env)); - } - - env->virt_enabled =3D enable; - - if (enable) { - /* - * The guest external interrupts from an interrupt controller are - * delivered only when the Guest/VM is running (i.e. V=3D1). This = means - * any guest external interrupt which is triggered while the Guest= /VM - * is not running (i.e. V=3D0) will be missed on QEMU resulting in= guest - * with sluggish response to serial console input and other I/O ev= ents. - * - * To solve this, we check and inject interrupt after setting V=3D= 1. - */ - riscv_cpu_update_mip(env, 0, 0); - } -} - int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts) { CPURISCVState *env =3D &cpu->env; @@ -715,7 +691,7 @@ void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, = uint32_t priv, } } =20 -void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv) +void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv, bool vir= t_en) { g_assert(newpriv <=3D PRV_M && newpriv !=3D PRV_RESERVED); =20 @@ -736,6 +712,28 @@ void riscv_cpu_set_mode(CPURISCVState *env, target_ulo= ng newpriv) * preemptive context switch. As a result, do both. */ env->load_res =3D -1; + + if (riscv_has_ext(env, RVH)) { + /* Flush the TLB on all virt mode changes. */ + if (env->virt_enabled !=3D virt_en) { + tlb_flush(env_cpu(env)); + } + + env->virt_enabled =3D virt_en; + if (virt_en) { + /* + * The guest external interrupts from an interrupt controller = are + * delivered only when the Guest/VM is running (i.e. V=3D1). T= his + * means any guest external interrupt which is triggered while= the + * Guest/VM is not running (i.e. V=3D0) will be missed on QEMU + * resulting in guest with sluggish response to serial console + * input and other I/O events. + * + * To solve this, we check and inject interrupt after setting = V=3D1. + */ + riscv_cpu_update_mip(env, 0, 0); + } + } } =20 /* @@ -1648,6 +1646,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) { RISCVCPU *cpu =3D RISCV_CPU(cs); CPURISCVState *env =3D &cpu->env; + bool virt =3D env->virt_enabled; bool write_gva =3D false; uint64_t s; =20 @@ -1778,7 +1777,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) =20 htval =3D env->guest_phys_fault_addr; =20 - riscv_cpu_set_virt_enabled(env, 0); + virt =3D false; } else { /* Trap into HS mode */ env->hstatus =3D set_field(env->hstatus, HSTATUS_SPV, fals= e); @@ -1799,7 +1798,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) env->htinst =3D tinst; env->pc =3D (env->stvec >> 2 << 2) + ((async && (env->stvec & 3) =3D=3D 1) ? cause * 4 : 0); - riscv_cpu_set_mode(env, PRV_S); + riscv_cpu_set_mode(env, PRV_S, virt); } else { /* handle the trap in M-mode */ if (riscv_has_ext(env, RVH)) { @@ -1815,7 +1814,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) mtval2 =3D env->guest_phys_fault_addr; =20 /* Trapping to M mode, virt is disabled */ - riscv_cpu_set_virt_enabled(env, 0); + virt =3D false; } =20 s =3D env->mstatus; @@ -1830,7 +1829,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) env->mtinst =3D tinst; env->pc =3D (env->mtvec >> 2 << 2) + ((async && (env->mtvec & 3) =3D=3D 1) ? cause * 4 : 0); - riscv_cpu_set_mode(env, PRV_M); + riscv_cpu_set_mode(env, PRV_M, virt); } =20 /* diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 2baf5bc3ca19..ec1408ba0fb1 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -264,7 +264,7 @@ void helper_cbo_inval(CPURISCVState *env, target_ulong = address) target_ulong helper_sret(CPURISCVState *env) { uint64_t mstatus; - target_ulong prev_priv, prev_virt; + target_ulong prev_priv, prev_virt =3D env->virt_enabled; =20 if (!(env->priv >=3D PRV_S)) { riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); @@ -307,11 +307,9 @@ target_ulong helper_sret(CPURISCVState *env) if (prev_virt) { riscv_cpu_swap_hypervisor_regs(env); } - - riscv_cpu_set_virt_enabled(env, prev_virt); } =20 - riscv_cpu_set_mode(env, prev_priv); + riscv_cpu_set_mode(env, prev_priv, prev_virt); =20 return retpc; } @@ -347,16 +345,13 @@ target_ulong helper_mret(CPURISCVState *env) mstatus =3D set_field(mstatus, MSTATUS_MPRV, 0); } env->mstatus =3D mstatus; - riscv_cpu_set_mode(env, prev_priv); - - if (riscv_has_ext(env, RVH)) { - if (prev_virt) { - riscv_cpu_swap_hypervisor_regs(env); - } =20 - riscv_cpu_set_virt_enabled(env, prev_virt); + if (riscv_has_ext(env, RVH) && prev_virt) { + riscv_cpu_swap_hypervisor_regs(env); } =20 + riscv_cpu_set_mode(env, prev_priv, prev_virt); + return retpc; } =20 --=20 2.34.1