From nobody Sun Nov 24 19:41:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.alibaba.com ARC-Seal: i=1; a=rsa-sha256; t=1720444781; cv=none; d=zohomail.com; s=zohoarc; b=GclOJ7u4VKone2ixGHNsleC0VF9Ym4qFbU2VIPofAf1guMKq8n/U2fITUF/T5hBwSKS0IJR8WC6Cn38wCNiqu/ut+j5AWeK7uT/aZfBbUsI23Da072JmS0fVeWMCJRm3Fo/6sGvpVcfcL0jNIq4YefRv+oBOYYWxI++bvi/JzPc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1720444781; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=O0IOyE9TbdMdefydvuFeYIhe0/fmQANDiIgHaap1df0=; b=g6Pjm/sHRdFsSxvBK73slqAmULRiN2yAfCyNjYu8xEs6flLgIDFSHtFM2UEgeKNFskdK+5sBniOszIOnB/TRoYAHdbHYUmc//27qHyOkWxfhoPnMJRjHPvswAEC90hKdnRmdOI2lemKEtGNw8J2oAU1sBuHT8pTx7lgVGgNAQM4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1720444781137494.6709612109423; Mon, 8 Jul 2024 06:19:41 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sQoGl-00049y-ID; Mon, 08 Jul 2024 09:19:03 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sQoGh-00048s-9E; Mon, 08 Jul 2024 09:19:00 -0400 Received: from out30-118.freemail.mail.aliyun.com ([115.124.30.118]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sQoGe-0003Nj-QX; Mon, 08 Jul 2024 09:18:59 -0400 Received: from L-PF1D6DP4-1208.hz.ali.com(mailfrom:zhiwei_liu@linux.alibaba.com fp:SMTPD_---0WA7d.Ij_1720444728) by smtp.aliyun-inc.com; Mon, 08 Jul 2024 21:18:49 +0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1720444731; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=O0IOyE9TbdMdefydvuFeYIhe0/fmQANDiIgHaap1df0=; b=jII/OZO9THCsPVXaeGv6wMqy+obJKq9KxQylk9T/RXNerh3NqLBUoNoK/mSdhZgjqyty/7IqFN60GJUUWMSy2lx5P3Z8X66ROo0XNdsdURXXWxw2sB9reLgazHpnO/VRt0Chmo52RPFsVj4+S1z4Kth9nYmcfwZBiZmiSeRG8Cg= X-Alimail-AntiSpam: AC=PASS; BC=-1|-1; BR=01201311R121e4; CH=green; DM=||false|; DS=||; FP=0|-1|-1|-1|0|-1|-1|-1; HT=maildocker-contentspam033023225041; MF=zhiwei_liu@linux.alibaba.com; NM=1; PH=DS; RN=11; SR=0; TI=SMTPD_---0WA7d.Ij_1720444728; From: LIU Zhiwei To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, palmer@dabbelt.com, alistair.francis@wdc.com, dbarboza@ventanamicro.com, liwei1518@gmail.com, bmeng.cn@gmail.com, zhiwei_liu@linux.alibaba.com, richard.henderson@linaro.org, philmd@linaro.org, TANG Tiancheng Subject: [PATCH v4 1/7] target/riscv: Add fw_dynamic_info32 for booting RV32 OpenSBI Date: Mon, 8 Jul 2024 21:16:38 +0800 Message-Id: <20240708131645.1345-2-zhiwei_liu@linux.alibaba.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20240708131645.1345-1-zhiwei_liu@linux.alibaba.com> References: <20240708131645.1345-1-zhiwei_liu@linux.alibaba.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=115.124.30.118; envelope-from=zhiwei_liu@linux.alibaba.com; helo=out30-118.freemail.mail.aliyun.com X-Spam_score_int: -174 X-Spam_score: -17.5 X-Spam_bar: ----------------- X-Spam_report: (-17.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, ENV_AND_HDR_SPF_MATCH=-0.5, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, UNPARSEABLE_RELAY=0.001, USER_IN_DEF_DKIM_WL=-7.5, USER_IN_DEF_SPF_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linux.alibaba.com) X-ZM-MESSAGEID: 1720444783260100005 Content-Type: text/plain; charset="utf-8" From: TANG Tiancheng RV32 OpenSBI need a fw_dynamic_info parameter with 32-bit fields instead of target_ulong. In RV64 QEMU, target_ulong is 64. So it is not right for booting RV32 OpenS= BI. We create a fw_dynmaic_info32 struct for this purpose. Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei Reviewed-by: Alistair Francis --- hw/riscv/boot.c | 35 ++++++++++++++++++++++----------- hw/riscv/sifive_u.c | 3 ++- include/hw/riscv/boot.h | 4 +++- include/hw/riscv/boot_opensbi.h | 29 +++++++++++++++++++++++++++ 4 files changed, 57 insertions(+), 14 deletions(-) diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index 47281ca853..1a2c1ff9e0 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -342,27 +342,33 @@ void riscv_load_fdt(hwaddr fdt_addr, void *fdt) rom_ptr_for_as(&address_space_memory, fdt_addr, fd= tsize)); } =20 -void riscv_rom_copy_firmware_info(MachineState *machine, hwaddr rom_base, - hwaddr rom_size, uint32_t reset_vec_size, +void riscv_rom_copy_firmware_info(MachineState *machine, + RISCVHartArrayState *harts, + hwaddr rom_base, hwaddr rom_size, + uint32_t reset_vec_size, uint64_t kernel_entry) { + struct fw_dynamic_info32 dinfo32; struct fw_dynamic_info dinfo; size_t dinfo_len; =20 - if (sizeof(dinfo.magic) =3D=3D 4) { - dinfo.magic =3D cpu_to_le32(FW_DYNAMIC_INFO_MAGIC_VALUE); - dinfo.version =3D cpu_to_le32(FW_DYNAMIC_INFO_VERSION); - dinfo.next_mode =3D cpu_to_le32(FW_DYNAMIC_INFO_NEXT_MODE_S); - dinfo.next_addr =3D cpu_to_le32(kernel_entry); + if (riscv_is_32bit(harts)) { + dinfo32.magic =3D cpu_to_le32(FW_DYNAMIC_INFO_MAGIC_VALUE); + dinfo32.version =3D cpu_to_le32(FW_DYNAMIC_INFO_VERSION); + dinfo32.next_mode =3D cpu_to_le32(FW_DYNAMIC_INFO_NEXT_MODE_S); + dinfo32.next_addr =3D cpu_to_le32(kernel_entry); + dinfo32.options =3D 0; + dinfo32.boot_hart =3D 0; + dinfo_len =3D sizeof(dinfo32); } else { dinfo.magic =3D cpu_to_le64(FW_DYNAMIC_INFO_MAGIC_VALUE); dinfo.version =3D cpu_to_le64(FW_DYNAMIC_INFO_VERSION); dinfo.next_mode =3D cpu_to_le64(FW_DYNAMIC_INFO_NEXT_MODE_S); dinfo.next_addr =3D cpu_to_le64(kernel_entry); + dinfo.options =3D 0; + dinfo.boot_hart =3D 0; + dinfo_len =3D sizeof(dinfo); } - dinfo.options =3D 0; - dinfo.boot_hart =3D 0; - dinfo_len =3D sizeof(dinfo); =20 /** * copy the dynamic firmware info. This information is specific to @@ -374,7 +380,10 @@ void riscv_rom_copy_firmware_info(MachineState *machin= e, hwaddr rom_base, exit(1); } =20 - rom_add_blob_fixed_as("mrom.finfo", &dinfo, dinfo_len, + rom_add_blob_fixed_as("mrom.finfo", + riscv_is_32bit(harts) ? + (void *)&dinfo32 : (void *)&dinfo, + dinfo_len, rom_base + reset_vec_size, &address_space_memory); } @@ -430,7 +439,9 @@ void riscv_setup_rom_reset_vec(MachineState *machine, R= ISCVHartArrayState *harts } rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), rom_base, &address_space_memory); - riscv_rom_copy_firmware_info(machine, rom_base, rom_size, sizeof(reset= _vec), + riscv_rom_copy_firmware_info(machine, harts, + rom_base, rom_size, + sizeof(reset_vec), kernel_entry); } =20 diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index af5f923f54..5010c3eadb 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -646,7 +646,8 @@ static void sifive_u_machine_init(MachineState *machine) rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), memmap[SIFIVE_U_DEV_MROM].base, &address_space_m= emory); =20 - riscv_rom_copy_firmware_info(machine, memmap[SIFIVE_U_DEV_MROM].base, + riscv_rom_copy_firmware_info(machine, &s->soc.u_cpus, + memmap[SIFIVE_U_DEV_MROM].base, memmap[SIFIVE_U_DEV_MROM].size, sizeof(reset_vec), kernel_entry); =20 diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h index a2e4ae9cb0..806256d23f 100644 --- a/include/hw/riscv/boot.h +++ b/include/hw/riscv/boot.h @@ -56,7 +56,9 @@ void riscv_setup_rom_reset_vec(MachineState *machine, RIS= CVHartArrayState *harts hwaddr rom_base, hwaddr rom_size, uint64_t kernel_entry, uint64_t fdt_load_addr); -void riscv_rom_copy_firmware_info(MachineState *machine, hwaddr rom_base, +void riscv_rom_copy_firmware_info(MachineState *machine, + RISCVHartArrayState *harts, + hwaddr rom_base, hwaddr rom_size, uint32_t reset_vec_size, uint64_t kernel_entry); diff --git a/include/hw/riscv/boot_opensbi.h b/include/hw/riscv/boot_opensb= i.h index 1b749663dc..18664a174b 100644 --- a/include/hw/riscv/boot_opensbi.h +++ b/include/hw/riscv/boot_opensbi.h @@ -58,4 +58,33 @@ struct fw_dynamic_info { target_long boot_hart; }; =20 +/** Representation dynamic info passed by previous booting stage */ +struct fw_dynamic_info32 { + /** Info magic */ + int32_t magic; + /** Info version */ + int32_t version; + /** Next booting stage address */ + int32_t next_addr; + /** Next booting stage mode */ + int32_t next_mode; + /** Options for OpenSBI library */ + int32_t options; + /** + * Preferred boot HART id + * + * It is possible that the previous booting stage uses same link + * address as the FW_DYNAMIC firmware. In this case, the relocation + * lottery mechanism can potentially overwrite the previous booting + * stage while other HARTs are still running in the previous booting + * stage leading to boot-time crash. To avoid this boot-time crash, + * the previous booting stage can specify last HART that will jump + * to the FW_DYNAMIC firmware as the preferred boot HART. + * + * To avoid specifying a preferred boot HART, the previous booting + * stage can set it to -1UL which will force the FW_DYNAMIC firmware + * to use the relocation lottery mechanism. + */ + int32_t boot_hart; +}; #endif --=20 2.43.0 From nobody Sun Nov 24 19:41:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.alibaba.com ARC-Seal: i=1; a=rsa-sha256; t=1720444781; cv=none; d=zohomail.com; s=zohoarc; b=fdP314xbQWLXTbm4evHqoLfVGy7iIufDHi0/HZyUxdkOdCWu7AHfdWzqhfBu7Hapab557wZoR+lQxE9rjTpmX8RFY8RHMU1XxAbRFfhOhzFr8KGP3c++/bcPqqYbA7Ccd7yPtdXlYVWmSIK3eUFmhm2Hv7PQeX2NG2/ZlAq/oMg= ARC-Message-Signature: i=1; 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charset="utf-8" From: TANG Tiancheng Ensure pmp_size is correctly determined using mxl for RV32 in RV64 QEMU. Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei Reviewed-by: Alistair Francis --- target/riscv/pmp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c index 9eea397e72..5e74b7220f 100644 --- a/target/riscv/pmp.c +++ b/target/riscv/pmp.c @@ -326,7 +326,7 @@ bool pmp_hart_has_privs(CPURISCVState *env, hwaddr addr, */ pmp_size =3D -(addr | TARGET_PAGE_MASK); } else { - pmp_size =3D sizeof(target_ulong); + pmp_size =3D 2 << riscv_cpu_mxl(env); } } else { pmp_size =3D size; --=20 2.43.0 From nobody Sun Nov 24 19:41:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.alibaba.com ARC-Seal: i=1; a=rsa-sha256; t=1720444830; cv=none; d=zohomail.com; s=zohoarc; b=D0k6ZK58WYmPqijvEsfVaVnc5ryI0K6d94IDAeHjg90r6Cpbc/siE9LuIJN9t1tNI2G9acFa1+5Uj8qzA4h5ssnSXXDsofT66RRKN7SShGcipTS8wrUj43ekwc8KV17jHV+FmVmgLXSpXUqDMM4xwHVERgTe30jOKI98QhMLa04= ARC-Message-Signature: i=1; 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charset="utf-8" From: TANG Tiancheng Ensure that riscv_cpu_sxl returns MXL_RV32 when runningRV32 in an RV64 QEMU. Signed-off-by: TANG Tiancheng Fixes: 05e6ca5e156 ("target/riscv: Ignore reserved bits in PTE for RV64") Reviewed-by: Liu Zhiwei Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 87742047ce..49de81be7e 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -693,8 +693,11 @@ static inline RISCVMXL riscv_cpu_sxl(CPURISCVState *en= v) #ifdef CONFIG_USER_ONLY return env->misa_mxl; #else - return get_field(env->mstatus, MSTATUS64_SXL); + if (env->misa_mxl !=3D MXL_RV32) { + return get_field(env->mstatus, MSTATUS64_SXL); + } #endif + return MXL_RV32; } #endif =20 --=20 2.43.0 From nobody Sun Nov 24 19:41:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.alibaba.com ARC-Seal: i=1; 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charset="utf-8" From: TANG Tiancheng Ensure correct bit width based on sxl when running RV32 on RV64 QEMU. This is required as MMU address translations run in S-mode. Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei Reviewed-by: Alistair Francis --- target/riscv/cpu_helper.c | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 6709622dd3..4f0ab90ac7 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -887,12 +887,14 @@ static int get_physical_address(CPURISCVState *env, h= waddr *physical, =20 CPUState *cs =3D env_cpu(env); int va_bits =3D PGSHIFT + levels * ptidxbits + widened; + int sxlen =3D 16 << riscv_cpu_sxl(env); + int sxlen_bytes =3D sxlen / 8; =20 if (first_stage =3D=3D true) { target_ulong mask, masked_msbs; =20 - if (TARGET_LONG_BITS > (va_bits - 1)) { - mask =3D (1L << (TARGET_LONG_BITS - (va_bits - 1))) - 1; + if (sxlen > (va_bits - 1)) { + mask =3D (1L << (sxlen - (va_bits - 1))) - 1; } else { mask =3D 0; } @@ -961,7 +963,7 @@ restart: =20 int pmp_prot; int pmp_ret =3D get_physical_address_pmp(env, &pmp_prot, pte_addr, - sizeof(target_ulong), + sxlen_bytes, MMU_DATA_LOAD, PRV_S); if (pmp_ret !=3D TRANSLATE_SUCCESS) { return TRANSLATE_PMP_FAIL; @@ -1113,7 +1115,7 @@ restart: * it is no longer valid and we must re-walk the page table. */ MemoryRegion *mr; - hwaddr l =3D sizeof(target_ulong), addr1; + hwaddr l =3D sxlen_bytes, addr1; mr =3D address_space_translate(cs->as, pte_addr, &addr1, &l, false, MEMTXATTRS_UNSPECIFIED); if (memory_region_is_ram(mr)) { @@ -1125,7 +1127,12 @@ restart: */ *pte_pa =3D pte =3D updated_pte; #else - target_ulong old_pte =3D qatomic_cmpxchg(pte_pa, pte, updated_= pte); + target_ulong old_pte; + if (riscv_cpu_sxl(env) =3D=3D MXL_RV32) { + old_pte =3D qatomic_cmpxchg((uint32_t *)pte_pa, pte, updat= ed_pte); + } else { + old_pte =3D qatomic_cmpxchg(pte_pa, pte, updated_pte); + } if (old_pte !=3D pte) { goto restart; } --=20 2.43.0 From nobody Sun Nov 24 19:41:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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charset="utf-8" From: TANG Tiancheng Ensure mcause high bit is correctly set by using 32-bit width for RV32 mode and 64-bit width for RV64 mode. Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei Reviewed-by: Alistair Francis --- target/riscv/cpu_helper.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 4f0ab90ac7..3eedb26cd9 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -1673,6 +1673,8 @@ void riscv_cpu_do_interrupt(CPUState *cs) target_ulong tinst =3D 0; target_ulong htval =3D 0; target_ulong mtval2 =3D 0; + int sxlen =3D 0; + int mxlen =3D 0; =20 if (!async) { /* set tval to badaddr for traps with address information */ @@ -1799,7 +1801,8 @@ void riscv_cpu_do_interrupt(CPUState *cs) s =3D set_field(s, MSTATUS_SPP, env->priv); s =3D set_field(s, MSTATUS_SIE, 0); env->mstatus =3D s; - env->scause =3D cause | ((target_ulong)async << (TARGET_LONG_BITS = - 1)); + sxlen =3D 16 << riscv_cpu_sxl(env); + env->scause =3D cause | ((target_ulong)async << (sxlen - 1)); env->sepc =3D env->pc; env->stval =3D tval; env->htval =3D htval; @@ -1830,7 +1833,8 @@ void riscv_cpu_do_interrupt(CPUState *cs) s =3D set_field(s, MSTATUS_MPP, env->priv); s =3D set_field(s, MSTATUS_MIE, 0); env->mstatus =3D s; - env->mcause =3D cause | ~(((target_ulong)-1) >> async); + mxlen =3D 16 << riscv_cpu_mxl(env); + env->mcause =3D cause | ((target_ulong)async << (mxlen - 1)); env->mepc =3D env->pc; env->mtval =3D tval; env->mtval2 =3D mtval2; --=20 2.43.0 From nobody Sun Nov 24 19:41:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.alibaba.com ARC-Seal: i=1; a=rsa-sha256; t=1720444906; cv=none; d=zohomail.com; s=zohoarc; b=T+XmLr273PqqdKN9tiMgGl9gt03uKqJ5ngImXiUQDFnMZAU7lUX4E49Eb+Kx38X5bc7FW51tBnh8UT/4LknorxTrOHrFCq2WVgxDOhDZSRMiqBsrdxRSxzoxn2UTtgmJQ93NEs95yoYUkvuItM7aeOgJvIGQylt/NFPGOuoVn7I= ARC-Message-Signature: i=1; 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charset="utf-8" From: TANG Tiancheng Add gdb XML files and adjust CPU initialization to allow running RV32 CPUs in RV64 QEMU. Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei Reviewed-by: Alistair Francis --- configs/targets/riscv64-softmmu.mak | 2 +- target/riscv/cpu.c | 17 +++++++++++++---- 2 files changed, 14 insertions(+), 5 deletions(-) diff --git a/configs/targets/riscv64-softmmu.mak b/configs/targets/riscv64-= softmmu.mak index 917980e63e..6c5de72e03 100644 --- a/configs/targets/riscv64-softmmu.mak +++ b/configs/targets/riscv64-softmmu.mak @@ -2,6 +2,6 @@ TARGET_ARCH=3Driscv64 TARGET_BASE_ARCH=3Driscv TARGET_SUPPORTS_MTTCG=3Dy TARGET_KVM_HAVE_GUEST_DEBUG=3Dy -TARGET_XML_FILES=3D gdb-xml/riscv-64bit-cpu.xml gdb-xml/riscv-32bit-fpu.xm= l gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-64bit-virtual.xml +TARGET_XML_FILES=3D gdb-xml/riscv-64bit-cpu.xml gdb-xml/riscv-32bit-fpu.xm= l gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-64bit-virtual.xml gdb-xml/riscv= -32bit-cpu.xml gdb-xml/riscv-32bit-virtual.xml # needed by boot.c TARGET_NEED_FDT=3Dy diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index a2640cf259..fdd0f10aa5 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -630,8 +630,10 @@ static void rv64e_bare_cpu_init(Object *obj) riscv_cpu_set_misa_ext(env, RVE); } =20 -#else /* !TARGET_RISCV64 */ +#endif /* !TARGET_RISCV64 */ =20 +#if defined(TARGET_RISCV32) || \ + (defined(TARGET_RISCV64) && !defined(CONFIG_USER_ONLY)) static void rv32_base_cpu_init(Object *obj) { RISCVCPU *cpu =3D RISCV_CPU(obj); @@ -2944,6 +2946,13 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { #if defined(TARGET_RISCV32) DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_ANY, MXL_RV32, riscv_any_cpu_= init), DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_MAX, MXL_RV32, riscv_max_cpu_= init), +#elif defined(TARGET_RISCV64) + DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_ANY, MXL_RV64, riscv_any_cpu_= init), + DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_MAX, MXL_RV64, riscv_max_cpu_= init), +#endif + +#if defined(TARGET_RISCV32) || \ + (defined(TARGET_RISCV64) && !defined(CONFIG_USER_ONLY)) DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE32, MXL_RV32, rv32_base_cpu_= init), DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_IBEX, MXL_RV32, rv32_ibex_cpu_= init), DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E31, MXL_RV32, rv32_sifive_e_= cpu_init), @@ -2951,9 +2960,9 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_U34, MXL_RV32, rv32_sifive_u_= cpu_init), DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV32I, MXL_RV32, rv32i_bare_cpu= _init), DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV32E, MXL_RV32, rv32e_bare_cpu= _init), -#elif defined(TARGET_RISCV64) - DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_ANY, MXL_RV64, riscv_any_cpu_= init), - DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_MAX, MXL_RV64, riscv_max_cpu_= init), +#endif + +#if defined(TARGET_RISCV64) DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE64, MXL_RV64, rv64_base_cpu_= init), DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E51, MXL_RV64, rv64_sifive_e_= cpu_init), DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_U54, MXL_RV64, rv64_sifive_u_= cpu_init), --=20 2.43.0 From nobody Sun Nov 24 19:41:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Mon, 08 Jul 2024 21:21:58 +0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1720444918; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=KogxXYbah1cU2iAB/kfLQdwgukHVYuAzaBwbvs2l0f8=; b=ZBTybYAxhvpbyuKuHRU9cd1as6js2ElOtq9ofKNfB5r7qo1ptVEmnvBUgoBIKhrtkJG5TD2UIvn0Uq4ZkogD6Rzcbbq38JyaAWS2e7jm7YLU/UnR3nNW7GrYVo+5V7agj9s1QDlbRulnSadObVifxim4TyUKtmGyFwFuQLnnoDs= X-Alimail-AntiSpam: AC=PASS; BC=-1|-1; BR=01201311R201e4; CH=green; DM=||false|; DS=||; FP=0|-1|-1|-1|0|-1|-1|-1; HT=maildocker-contentspam033037067113; MF=zhiwei_liu@linux.alibaba.com; NM=1; PH=DS; RN=11; SR=0; TI=SMTPD_---0WA7d09i_1720444917; From: LIU Zhiwei To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, palmer@dabbelt.com, alistair.francis@wdc.com, dbarboza@ventanamicro.com, liwei1518@gmail.com, bmeng.cn@gmail.com, zhiwei_liu@linux.alibaba.com, richard.henderson@linaro.org, philmd@linaro.org, TANG Tiancheng Subject: [PATCH v4 7/7] tests/avocado: Add an avocado test for riscv64 Date: Mon, 8 Jul 2024 21:16:44 +0800 Message-Id: <20240708131645.1345-8-zhiwei_liu@linux.alibaba.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20240708131645.1345-1-zhiwei_liu@linux.alibaba.com> References: <20240708131645.1345-1-zhiwei_liu@linux.alibaba.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" From: TANG Tiancheng To regularly test booting Linux with rv32 on QEMU RV64, we have added a test to boot_linux_console.py to retrieve cpuinfo and verify if it shows 'rv32' when using RV64 to boot rv32 CPUs. Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei Acked-by: Alistair Francis Reviewed-by: Alistair Francis --- tests/avocado/boot_linux_console.py | 37 +++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/tests/avocado/boot_linux_console.py b/tests/avocado/boot_linux= _console.py index c35fc5e9ba..f333253f69 100644 --- a/tests/avocado/boot_linux_console.py +++ b/tests/avocado/boot_linux_console.py @@ -12,6 +12,7 @@ import lzma import gzip import shutil +import time =20 from avocado import skip from avocado import skipUnless @@ -1545,3 +1546,39 @@ def test_xtensa_lx60(self): """ tar_hash =3D '49e88d9933742f0164b60839886c9739cb7a0d34' self.do_test_advcal_2018('02', tar_hash, 'santas-sleigh-ride.elf') + + def test_riscv64_virt_rv32i(self): + """ + :avocado: tags=3Darch:riscv64 + :avocado: tags=3Dmachine:virt + :avocado: tags=3Dcpu:rv32 + """ + kernel_url =3D ('https://github.com/romanheros/rv32-linux/raw/mast= er/' + 'Image32.xz') + kernel_hash =3D 'a7ced5c38722481e0821b7cd70719cf53e46c13b' + kernel_path_xz =3D self.fetch_asset(kernel_url, asset_hash=3Dkerne= l_hash) + + kernel_path =3D os.path.join(self.workdir, 'kernel.riscv32') + archive.lzma_uncompress(kernel_path_xz, kernel_path) + + rootfs_url =3D ('https://github.com/romanheros/rv32-linux/raw/mast= er/' + 'rootfs.ext2.xz') + rootfs_hash =3D 'dc25ab9d4b233e8e0bcf7eb220d56fd2008fe263' + rootfs_path_xz =3D self.fetch_asset(rootfs_url, asset_hash=3Drootf= s_hash) + + rootfs_path =3D os.path.join(self.workdir, 'rootfs.riscv32') + archive.lzma_uncompress(rootfs_path_xz, rootfs_path) + + self.vm.set_console() + kernel_command_line =3D 'root=3D/dev/vda ro console=3DttyS0' + self.vm.add_args('-kernel', kernel_path, + '-append', kernel_command_line, + '-drive', f'file=3D{rootfs_path},format=3Draw,id= =3Dhd0,if=3Dnone', + '-device', 'virtio-blk-device,drive=3Dhd0') + self.vm.launch() + + console_pattern =3D 'Welcome to Buildroot' + self.wait_for_console_pattern(console_pattern) + exec_command(self, 'root') + time.sleep(0.1) + exec_command_and_wait_for_pattern(self, 'cat /proc/cpuinfo', 'rv32= i') --=20 2.43.0