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Tsirkin" , Igor Mammedov , Ani Sinha , Sunil V L Subject: [PATCH v2 1/9] hw/riscv/virt-acpi-build.c: Add namespace devices for PLIC and APLIC Date: Mon, 8 Jul 2024 17:17:33 +0530 Message-ID: <20240708114741.3499585-2-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240708114741.3499585-1-sunilvl@ventanamicro.com> References: <20240708114741.3499585-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::12c; envelope-from=sunilvl@ventanamicro.com; helo=mail-il1-x12c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1720439411950100007 Content-Type: text/plain; charset="utf-8" PLIC and APLIC should be in namespace as well. So, add them using the defined HID. Signed-off-by: Sunil V L Acked-by: Alistair Francis --- hw/riscv/virt-acpi-build.c | 47 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c index 0925528160..87fe882af0 100644 --- a/hw/riscv/virt-acpi-build.c +++ b/hw/riscv/virt-acpi-build.c @@ -141,6 +141,52 @@ static void acpi_dsdt_add_cpus(Aml *scope, RISCVVirtSt= ate *s) } } =20 +static void acpi_dsdt_add_plic_aplic(Aml *scope, RISCVVirtState *s) +{ + MachineState *ms =3D MACHINE(s); + uint64_t plic_aplic_addr; + uint32_t gsi_base; + uint8_t socket; + + if (s->aia_type =3D=3D VIRT_AIA_TYPE_NONE) { + /* PLICs */ + for (socket =3D 0; socket < riscv_socket_count(ms); socket++) { + plic_aplic_addr =3D s->memmap[VIRT_PLIC].base + + s->memmap[VIRT_PLIC].size * socket; + gsi_base =3D VIRT_IRQCHIP_NUM_SOURCES * socket; + Aml *dev =3D aml_device("IC%.02X", socket); + aml_append(dev, aml_name_decl("_HID", aml_string("RSCV0001"))); + aml_append(dev, aml_name_decl("_UID", aml_int(socket))); + aml_append(dev, aml_name_decl("_GSB", aml_int(gsi_base))); + + Aml *crs =3D aml_resource_template(); + aml_append(crs, aml_memory32_fixed(plic_aplic_addr, + s->memmap[VIRT_PLIC].size, + AML_READ_WRITE)); + aml_append(dev, aml_name_decl("_CRS", crs)); + aml_append(scope, dev); + } + } else { + /* APLICs */ + for (socket =3D 0; socket < riscv_socket_count(ms); socket++) { + plic_aplic_addr =3D s->memmap[VIRT_APLIC_S].base + + s->memmap[VIRT_APLIC_S].size * socket; + gsi_base =3D VIRT_IRQCHIP_NUM_SOURCES * socket; + Aml *dev =3D aml_device("IC%.02X", socket); + aml_append(dev, aml_name_decl("_HID", aml_string("RSCV0002"))); + aml_append(dev, aml_name_decl("_UID", aml_int(socket))); + aml_append(dev, aml_name_decl("_GSB", aml_int(gsi_base))); + + Aml *crs =3D aml_resource_template(); + aml_append(crs, aml_memory32_fixed(plic_aplic_addr, + s->memmap[VIRT_APLIC_S].siz= e, + AML_READ_WRITE)); + aml_append(dev, aml_name_decl("_CRS", crs)); + aml_append(scope, dev); + } + } +} + static void acpi_dsdt_add_uart(Aml *scope, const MemMapEntry *uart_memmap, uint32_t uart_irq) @@ -411,6 +457,7 @@ static void build_dsdt(GArray *table_data, =20 socket_count =3D riscv_socket_count(ms); =20 + acpi_dsdt_add_plic_aplic(scope, s); acpi_dsdt_add_uart(scope, &memmap[VIRT_UART0], UART0_IRQ); =20 if (socket_count =3D=3D 1) { --=20 2.43.0